5 files changed, 9 insertions, 8 deletions

diff --git a/lisp/progmodes/ada-xref.el b/lisp/progmodes/ada-xref.el
index f30457992a3..9c53b1a9e23 100644
--- a/lisp/progmodes/ada-xref.el
+++ b/lisp/progmodes/ada-xref.el
@@ -1533,7 +1533,7 @@ the project file."
   ;;      .ali file for a spec file.  If we are, go to step 3.
   ;;   3- If the file is not found or step 2 failed:
   ;;      find the name of the "other file", ie the body, and look
-  ;;      for its associated .ali file by subtituing the extension
+  ;;      for its associated .ali file by subtituting the extension
   ;;
   ;; We must also handle the case of separate packages and subprograms:
   ;;   4- If no ali file was found, we try to modify the file name by removing
diff --git a/lisp/progmodes/cc-engine.el b/lisp/progmodes/cc-engine.el
index 57ee3943bbe..2d18498d6f4 100644
--- a/lisp/progmodes/cc-engine.el
+++ b/lisp/progmodes/cc-engine.el
@@ -2594,7 +2594,7 @@ comment at the start of cc-engine.el for more info."
         mstart)               ; start of a macro.
 
     (save-excursion
-      ;; Each time round the following loop, we enter a succesively deeper
+      ;; Each time round the following loop, we enter a successively deeper
       ;; level of brace/paren nesting.  (Except sometimes we "continue at
       ;; the existing level".)  `pa+1' is a pos inside an opening
       ;; brace/paren/bracket, usually just after it.
diff --git a/lisp/progmodes/js.el b/lisp/progmodes/js.el
index f0c86265232..808d17dff54 100644
--- a/lisp/progmodes/js.el
+++ b/lisp/progmodes/js.el
@@ -369,7 +369,8 @@ Match group 1 is the name of the macro.")
 ;; must be h-end.
 ;;
 ;; js--pitem instances are never modified (with the exception
-;; of the b-end field). Instead, modified copies are added at subseqnce parse points.
+;; of the b-end field). Instead, modified copies are added at
+;; subsequence parse points.
 ;; (The exception for b-end and its caveats is described below.)
 ;;
 
diff --git a/lisp/progmodes/meta-mode.el b/lisp/progmodes/meta-mode.el
index d0a34179cc8..53ae22b9908 100644
--- a/lisp/progmodes/meta-mode.el
+++ b/lisp/progmodes/meta-mode.el
@@ -384,7 +384,7 @@ Each entry is a list with the following elements:
 1. Regexp matching the preceding text.
 2. A number indicating the subgroup in the regexp containing the text.
 3. A function returning an alist of possible completions.
-4. Text to append after a succesful completion (if any).
+4. Text to append after a successful completion (if any).
 
 Or alternatively:
 1. Regexp matching the preceding text.
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index 52e7b6e2429..f68398c6459 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -1423,7 +1423,7 @@ If set will become buffer local.")
       ["AUTOSENSE"                      (describe-function 'verilog-auto-sense)
        :help            "Help on AUTOSENSE - sensitivity lists for always blocks"]
       ["AUTOTIEOFF"                     (describe-function 'verilog-auto-tieoff)
-       :help            "Help on AUTOTIEOFF - tieing off unused outputs"]
+       :help            "Help on AUTOTIEOFF - tying off unused outputs"]
       ["AUTOUNUSED"                     (describe-function 'verilog-auto-unused)
        :help            "Help on AUTOUNUSED - terminating unused inputs"]
       ["AUTOWIRE"                       (describe-function 'verilog-auto-wire)
@@ -1667,7 +1667,7 @@ This speeds up complicated regexp matches."
   ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
   (save-excursion
     (goto-char (point-min))
-    (while (re-search-forward "[ \t]+$" nil t)  ;; Not syntatic WS as no formfeed
+    (while (re-search-forward "[ \t]+$" nil t)  ;; Not syntactic WS as no formfeed
       (replace-match "" nil nil))))
 
 (defvar compile-command)
@@ -11725,7 +11725,7 @@ this is a recent change.  To control this behavior, see
 `verilog-auto-reset-widths'.
 
 AUTORESET ties signals to deasserted, which is presumed to be zero.
-Signals that match `verilog-active-low-regexp' will be deasserted by tieing
+Signals that match `verilog-active-low-regexp' will be deasserted by tying
 them to a one.
 
 An example:
@@ -11816,7 +11816,7 @@ finds all outputs in the module, and if that input is not otherwise declared
 as a register or wire, creates a tieoff.
 
 AUTORESET ties signals to deasserted, which is presumed to be zero.
-Signals that match `verilog-active-low-regexp' will be deasserted by tieing
+Signals that match `verilog-active-low-regexp' will be deasserted by tying
 them to a one.
 
 You can add signals you do not want included in AUTOTIEOFF with