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-rw-r--r--lisp/progmodes/verilog-mode.el1035
1 files changed, 517 insertions, 518 deletions
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index eeed4c0d7c8..8ddd262af3e 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -1171,7 +1171,7 @@ inputs. This is then used by an upper module:
1171 output OUT_t o; 1171 output OUT_t o;
1172 endmodule 1172 endmodule
1173 1173
1174 module ExampInst; 1174 module ExampParamVal1;
1175 /*AUTOOUTPUT*/ 1175 /*AUTOOUTPUT*/
1176 // Beginning of automatic outputs 1176 // Beginning of automatic outputs
1177 output OUT_t o; 1177 output OUT_t o;
@@ -1182,8 +1182,13 @@ inputs. This is then used by an upper module:
1182 ,.OUT_t(upper_t)) 1182 ,.OUT_t(upper_t))
1183 instName 1183 instName
1184 (/*AUTOINST*/ 1184 (/*AUTOINST*/
1185 .i (i[WIDTH-1:0]), 1185 .o (o),
1186 .o (o)); 1186 .i (i[WIDTH-1:0]));
1187 endmodule
1188
1189 // Local Variables:
1190 // verilog-typedef-regexp: \"_t$\"
1191 // End:
1187 1192
1188Note even though WIDTH=10, the AUTOINST has left the parameter as 1193Note even though WIDTH=10, the AUTOINST has left the parameter as
1189a symbolic name. Likewise the OUT_t is preserved as the name 1194a symbolic name. Likewise the OUT_t is preserved as the name
@@ -1192,7 +1197,7 @@ from the instantiated module.
1192If `verilog-auto-inst-param-value' is set, this will 1197If `verilog-auto-inst-param-value' is set, this will
1193instead expand to: 1198instead expand to:
1194 1199
1195 module ExampInst; 1200 module ExampParamVal1;
1196 /*AUTOOUTPUT*/ 1201 /*AUTOOUTPUT*/
1197 // Beginning of automatic outputs 1202 // Beginning of automatic outputs
1198 output upper_t o; 1203 output upper_t o;
@@ -1203,8 +1208,8 @@ instead expand to:
1203 ,.OUT_t(upper_t)) 1208 ,.OUT_t(upper_t))
1204 instName 1209 instName
1205 (/*AUTOINST*/ 1210 (/*AUTOINST*/
1206 .i (i[9:0]), 1211 .o (o),
1207 .o (o)); 1212 .i (i[9:0]));
1208 1213
1209Note that the instantiation now has \"i[9:0]\" as the WIDTH 1214Note that the instantiation now has \"i[9:0]\" as the WIDTH
1210was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT 1215was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
@@ -8977,11 +8982,11 @@ component library to determine connectivity of the design.
8977One work around for this problem is to manually create // Inputs and // 8982One work around for this problem is to manually create // Inputs and //
8978Outputs comments above subcell signals, for example: 8983Outputs comments above subcell signals, for example:
8979 8984
8980 module ModuleName ( 8985 submod SubModuleName (
8981 // Outputs 8986 // Outputs
8982 .out (out), 8987 .out (out),
8983 // Inputs 8988 // Inputs
8984 .in (in));" 8989 .in (in));"
8985 (save-excursion 8990 (save-excursion
8986 (let ((end-mod-point (verilog-get-end-of-defun)) 8991 (let ((end-mod-point (verilog-get-end-of-defun))
8987 st-point end-inst-point par-values 8992 st-point end-inst-point par-values
@@ -10848,32 +10853,33 @@ support adding new ports. You may wish to delete older ports yourself.
10848 10853
10849For example: 10854For example:
10850 10855
10851 module ExampInject (i, o); 10856 module ExampInject (i, o);
10852 input i; 10857 input i;
10853 input j; 10858 input j;
10854 output o; 10859 output o;
10855 always @ (i or j) 10860 always @ (i or j)
10856 o = i | j; 10861 o = i | j;
10857 InstModule instName 10862 InstModule instName
10858 (.foobar(baz), 10863 (.foobar(baz),
10859 j(j)); 10864 .j(j));
10860 endmodule 10865 endmodule
10861 10866
10862Typing \\[verilog-inject-auto] will make this into: 10867Typing \\[verilog-inject-auto] (with an appropriate submodule not
10863 10868shown) will make this into:
10864 module ExampInject (i, o/*AUTOARG*/ 10869
10865 // Inputs 10870 module ExampInject (i, o/*AUTOARG*/
10866 j); 10871 // Inputs
10867 input i; 10872 j);
10868 output o; 10873 input i;
10869 always @ (/*AS*/i or j) 10874 output o;
10870 o = i | j; 10875 always @ (/*AS*/i or j)
10871 InstModule instName 10876 o = i | j;
10877 InstModule instName
10872 (.foobar(baz), 10878 (.foobar(baz),
10873 /*AUTOINST*/ 10879 /*AUTOINST*/
10874 // Outputs 10880 // Outputs
10875 j(j)); 10881 j(j));
10876 endmodule" 10882 endmodule"
10877 (interactive) 10883 (interactive)
10878 (verilog-auto t)) 10884 (verilog-auto t))
10879 10885
@@ -11184,22 +11190,21 @@ Limitations:
11184 11190
11185For example: 11191For example:
11186 11192
11187 module ExampArg (/*AUTOARG*/); 11193 module ExampArg (/*AUTOARG*/);
11188 input i; 11194 input i;
11189 output o; 11195 output o;
11190 endmodule 11196 endmodule
11191 11197
11192Typing \\[verilog-auto] will make this into: 11198Typing \\[verilog-auto] will make this into:
11193 11199
11194 module ExampArg (/*AUTOARG*/ 11200 module ExampArg (/*AUTOARG*/
11195 // Outputs 11201 // Outputs
11196 o, 11202 o,
11197 // Inputs 11203 // Inputs
11198 i 11204 i);
11199 ); 11205 input i;
11200 input i; 11206 output o;
11201 output o; 11207 endmodule
11202 endmodule
11203 11208
11204The argument declarations may be printed in declaration order to 11209The argument declarations may be printed in declaration order to
11205best suit order based instantiations, or alphabetically, based on 11210best suit order based instantiations, or alphabetically, based on
@@ -11548,33 +11553,33 @@ Limitations:
11548 11553
11549For example, first take the submodule InstModule.v: 11554For example, first take the submodule InstModule.v:
11550 11555
11551 module InstModule (o,i); 11556 module InstModule (o,i);
11552 output [31:0] o; 11557 output [31:0] o;
11553 input i; 11558 input i;
11554 wire [31:0] o = {32{i}}; 11559 wire [31:0] o = {32{i}};
11555 endmodule 11560 endmodule
11556 11561
11557This is then used in an upper level module: 11562This is then used in an upper level module:
11558 11563
11559 module ExampInst (o,i); 11564 module ExampInst (o,i);
11560 output o; 11565 output o;
11561 input i; 11566 input i;
11562 InstModule instName 11567 InstModule instName
11563 (/*AUTOINST*/); 11568 (/*AUTOINST*/);
11564 endmodule 11569 endmodule
11565 11570
11566Typing \\[verilog-auto] will make this into: 11571Typing \\[verilog-auto] will make this into:
11567 11572
11568 module ExampInst (o,i); 11573 module ExampInst (o,i);
11569 output o; 11574 output o;
11570 input i; 11575 input i;
11571 InstModule instName 11576 InstModule instName
11572 (/*AUTOINST*/ 11577 (/*AUTOINST*/
11573 // Outputs 11578 // Outputs
11574 .ov (ov[31:0]), 11579 .o (o[31:0]),
11575 // Inputs 11580 // Inputs
11576 .i (i)); 11581 .i (i));
11577 endmodule 11582 endmodule
11578 11583
11579Where the list of inputs and outputs came from the inst module. 11584Where the list of inputs and outputs came from the inst module.
11580 11585
@@ -11595,12 +11600,12 @@ Exceptions:
11595 you have the appropriate // Input or // Output comment, and exactly the 11600 you have the appropriate // Input or // Output comment, and exactly the
11596 same line formatting as AUTOINST itself uses. 11601 same line formatting as AUTOINST itself uses.
11597 11602
11598 InstModule instName 11603 InstModule instName
11599 (// Inputs 11604 (// Inputs
11600 .i (my_i_dont_mess_with_it), 11605 .i (my_i_dont_mess_with_it),
11601 /*AUTOINST*/ 11606 /*AUTOINST*/
11602 // Outputs 11607 // Outputs
11603 .ov (ov[31:0])); 11608 .o (o[31:0]));
11604 11609
11605 11610
11606Templates: 11611Templates:
@@ -11608,10 +11613,10 @@ Templates:
11608 For multiple instantiations based upon a single template, create a 11613 For multiple instantiations based upon a single template, create a
11609 commented out template: 11614 commented out template:
11610 11615
11611 /* InstModule AUTO_TEMPLATE ( 11616 /* InstModule AUTO_TEMPLATE (
11612 .sig3 (sigz[]), 11617 .sig3 (sigz[]),
11613 ); 11618 );
11614 */ 11619 */
11615 11620
11616 Templates go ABOVE the instantiation(s). When an instantiation is 11621 Templates go ABOVE the instantiation(s). When an instantiation is
11617 expanded `verilog-mode' simply searches up for the closest template. 11622 expanded `verilog-mode' simply searches up for the closest template.
@@ -11655,19 +11660,19 @@ Templates:
11655 11660
11656 For example: 11661 For example:
11657 11662
11658 /* InstModule AUTO_TEMPLATE ( 11663 /* InstModule AUTO_TEMPLATE (
11659 .ptl_bus (ptl_busnew[]), 11664 .ptl_bus (ptl_busnew[]),
11660 ); 11665 );
11661 */ 11666 */
11662 InstModule ms2m (/*AUTOINST*/); 11667 InstModule ms2m (/*AUTOINST*/);
11663 11668
11664 Typing \\[verilog-auto] will make this into: 11669 Typing \\[verilog-auto] will make this into:
11665 11670
11666 InstModule ms2m (/*AUTOINST*/ 11671 InstModule ms2m (/*AUTOINST*/
11667 // Outputs 11672 // Outputs
11668 .NotInTemplate (NotInTemplate), 11673 .NotInTemplate (NotInTemplate),
11669 .ptl_bus (ptl_busnew[3:0]), // Templated 11674 .ptl_bus (ptl_busnew[3:0]), // Templated
11670 .... 11675 ....
11671 11676
11672 11677
11673Multiple Module Templates: 11678Multiple Module Templates:
@@ -11675,13 +11680,13 @@ Multiple Module Templates:
11675 The same template lines can be applied to multiple modules with 11680 The same template lines can be applied to multiple modules with
11676 the syntax as follows: 11681 the syntax as follows:
11677 11682
11678 /* InstModuleA AUTO_TEMPLATE 11683 /* InstModuleA AUTO_TEMPLATE
11679 InstModuleB AUTO_TEMPLATE 11684 InstModuleB AUTO_TEMPLATE
11680 InstModuleC AUTO_TEMPLATE 11685 InstModuleC AUTO_TEMPLATE
11681 InstModuleD AUTO_TEMPLATE ( 11686 InstModuleD AUTO_TEMPLATE (
11682 .ptl_bus (ptl_busnew[]), 11687 .ptl_bus (ptl_busnew[]),
11683 ); 11688 );
11684 */ 11689 */
11685 11690
11686 Note there is only one AUTO_TEMPLATE opening parenthesis. 11691 Note there is only one AUTO_TEMPLATE opening parenthesis.
11687 11692
@@ -11690,11 +11695,11 @@ Multiple Module Templates:
11690 It is common to instantiate a cell multiple times, so templates make it 11695 It is common to instantiate a cell multiple times, so templates make it
11691 trivial to substitute part of the cell name into the connection name. 11696 trivial to substitute part of the cell name into the connection name.
11692 11697
11693 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> ( 11698 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
11694 .sig1 (sigx[@]), 11699 .sig1 (sigx[@]),
11695 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]), 11700 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
11696 ); 11701 );
11697 */ 11702 */
11698 11703
11699 If no regular expression is provided immediately after the AUTO_TEMPLATE 11704 If no regular expression is provided immediately after the AUTO_TEMPLATE
11700 keyword, then the @ character in any connection names will be replaced 11705 keyword, then the @ character in any connection names will be replaced
@@ -11712,49 +11717,49 @@ Multiple Module Templates:
11712 11717
11713 For example: 11718 For example:
11714 11719
11715 /* InstModule AUTO_TEMPLATE ( 11720 /* InstModule AUTO_TEMPLATE (
11716 .ptl_mapvalidx (ptl_mapvalid[@]), 11721 .ptl_mapvalidx (ptl_mapvalid[@]),
11717 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]), 11722 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11718 ); 11723 );
11719 */ 11724 */
11720 InstModule ms2m (/*AUTOINST*/); 11725 InstModule ms2m (/*AUTOINST*/);
11721 11726
11722 Typing \\[verilog-auto] will make this into: 11727 Typing \\[verilog-auto] will make this into:
11723 11728
11724 InstModule ms2m (/*AUTOINST*/ 11729 InstModule ms2m (/*AUTOINST*/
11725 // Outputs 11730 // Outputs
11726 .ptl_mapvalidx (ptl_mapvalid[2]), 11731 .ptl_mapvalidx (ptl_mapvalid[2]),
11727 .ptl_mapvalidp1x (ptl_mapvalid[3])); 11732 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11728 11733
11729 Note the @ character was replaced with the 2 from \"ms2m\". 11734 Note the @ character was replaced with the 2 from \"ms2m\".
11730 11735
11731 Alternatively, using a regular expression for @: 11736 Alternatively, using a regular expression for @:
11732 11737
11733 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" ( 11738 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11734 .ptl_mapvalidx (@_ptl_mapvalid), 11739 .ptl_mapvalidx (@_ptl_mapvalid),
11735 .ptl_mapvalidp1x (ptl_mapvalid_@), 11740 .ptl_mapvalidp1x (ptl_mapvalid_@),
11736 ); 11741 );
11737 */ 11742 */
11738 InstModule ms2_FOO (/*AUTOINST*/); 11743 InstModule ms2_FOO (/*AUTOINST*/);
11739 InstModule ms2_BAR (/*AUTOINST*/); 11744 InstModule ms2_BAR (/*AUTOINST*/);
11740 11745
11741 Typing \\[verilog-auto] will make this into: 11746 Typing \\[verilog-auto] will make this into:
11742 11747
11743 InstModule ms2_FOO (/*AUTOINST*/ 11748 InstModule ms2_FOO (/*AUTOINST*/
11744 // Outputs 11749 // Outputs
11745 .ptl_mapvalidx (FOO_ptl_mapvalid), 11750 .ptl_mapvalidx (FOO_ptl_mapvalid),
11746 .ptl_mapvalidp1x (ptl_mapvalid_FOO)); 11751 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11747 InstModule ms2_BAR (/*AUTOINST*/ 11752 InstModule ms2_BAR (/*AUTOINST*/
11748 // Outputs 11753 // Outputs
11749 .ptl_mapvalidx (BAR_ptl_mapvalid), 11754 .ptl_mapvalidx (BAR_ptl_mapvalid),
11750 .ptl_mapvalidp1x (ptl_mapvalid_BAR)); 11755 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11751 11756
11752 11757
11753Regexp Templates: 11758Regexp Templates:
11754 11759
11755 A template entry of the form 11760 A template entry of the form
11756 11761
11757 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]), 11762 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11758 11763
11759 will apply an Emacs style regular expression search for any port beginning 11764 will apply an Emacs style regular expression search for any port beginning
11760 in pci_req followed by numbers and ending in _l and connecting that to 11765 in pci_req followed by numbers and ending in _l and connecting that to
@@ -11766,13 +11771,13 @@ Regexp Templates:
11766 completely different -- still use \\1 there!) Thus this is the same as 11771 completely different -- still use \\1 there!) Thus this is the same as
11767 the above template: 11772 the above template:
11768 11773
11769 .pci_req@_l (pci_req_jtag_[\\1]), 11774 .pci_req@_l (pci_req_jtag_[\\1]),
11770 11775
11771 Here's another example to remove the _l, useful when naming conventions 11776 Here's another example to remove the _l, useful when naming conventions
11772 specify _ alone to mean active low. Note the use of [] to keep the bus 11777 specify _ alone to mean active low. Note the use of [] to keep the bus
11773 subscript: 11778 subscript:
11774 11779
11775 .\\(.*\\)_l (\\1_[]), 11780 .\\(.*\\)_l (\\1_[]),
11776 11781
11777Lisp Templates: 11782Lisp Templates:
11778 11783
@@ -11788,21 +11793,21 @@ Lisp Templates:
11788 There are special variables defined that are useful in these 11793 There are special variables defined that are useful in these
11789 Lisp functions: 11794 Lisp functions:
11790 11795
11791 vl-name Name portion of the input/output port. 11796 vl-name Name portion of the input/output port.
11792 vl-bits Bus bits portion of the input/output port (`[2:0]'). 11797 vl-bits Bus bits portion of the input/output port (`[2:0]').
11793 vl-mbits Multidimensional array bits for port (`[2:0][3:0]'). 11798 vl-mbits Multidimensional array bits for port (`[2:0][3:0]').
11794 vl-width Width of the input/output port (`3' for [2:0]). 11799 vl-width Width of the input/output port (`3' for [2:0]).
11795 May be a (...) expression if bits isn't a constant. 11800 May be a (...) expression if bits isn't a constant.
11796 vl-dir Direction of the pin input/output/inout/interface. 11801 vl-dir Direction of the pin input/output/inout/interface.
11797 vl-modport The modport, if an interface with a modport. 11802 vl-modport The modport, if an interface with a modport.
11798 vl-cell-type Module name/type of the cell (`InstModule'). 11803 vl-cell-type Module name/type of the cell (`InstModule').
11799 vl-cell-name Instance name of the cell (`instName'). 11804 vl-cell-name Instance name of the cell (`instName').
11800 11805
11801 Normal Lisp variables may be used in expressions. See 11806 Normal Lisp variables may be used in expressions. See
11802 `verilog-read-defines' which can set vh-{definename} variables for use 11807 `verilog-read-defines' which can set vh-{definename} variables for use
11803 here. Also, any comments of the form: 11808 here. Also, any comments of the form:
11804 11809
11805 /*AUTO_LISP(setq foo 1)*/ 11810 /*AUTO_LISP(setq foo 1)*/
11806 11811
11807 will evaluate any Lisp expression inside the parenthesis between the 11812 will evaluate any Lisp expression inside the parenthesis between the
11808 beginning of the buffer and the point of the AUTOINST. This allows 11813 beginning of the buffer and the point of the AUTOINST. This allows
@@ -11932,28 +11937,27 @@ output.
11932 11937
11933For example, first take the submodule InstModule.v: 11938For example, first take the submodule InstModule.v:
11934 11939
11935 module InstModule (o,i); 11940 module InstModule (o,i);
11936 parameter PAR; 11941 parameter PAR;
11937 endmodule 11942 endmodule
11938 11943
11939This is then used in an upper level module: 11944This is then used in an upper level module:
11940 11945
11941 module ExampInst (o,i); 11946 module ExampInstParam (o,i);
11942 parameter PAR; 11947 parameter PAR;
11943 InstModule #(/*AUTOINSTPARAM*/) 11948 InstModule #(/*AUTOINSTPARAM*/)
11944 instName (/*AUTOINST*/); 11949 instName (/*AUTOINST*/);
11945 endmodule 11950 endmodule
11946 11951
11947Typing \\[verilog-auto] will make this into: 11952Typing \\[verilog-auto] will make this into:
11948 11953
11949 module ExampInst (o,i); 11954 module ExampInstParam (o,i);
11950 output o; 11955 parameter PAR;
11951 input i; 11956 InstModule #(/*AUTOINSTPARAM*/
11952 InstModule #(/*AUTOINSTPARAM*/ 11957 // Parameters
11953 // Parameters 11958 .PAR (PAR))
11954 .PAR (PAR)); 11959 instName (/*AUTOINST*/);
11955 instName (/*AUTOINST*/); 11960 endmodule
11956 endmodule
11957 11961
11958Where the list of parameter connections come from the inst module. 11962Where the list of parameter connections come from the inst module.
11959 11963
@@ -12035,24 +12039,24 @@ Limitations:
12035 12039
12036An example: 12040An example:
12037 12041
12038 module ExampReg (o,i); 12042 module ExampReg (o,i);
12039 output o; 12043 output o;
12040 input i; 12044 input i;
12041 /*AUTOREG*/ 12045 /*AUTOREG*/
12042 always o = i; 12046 always o = i;
12043 endmodule 12047 endmodule
12044 12048
12045Typing \\[verilog-auto] will make this into: 12049Typing \\[verilog-auto] will make this into:
12046 12050
12047 module ExampReg (o,i); 12051 module ExampReg (o,i);
12048 output o; 12052 output o;
12049 input i; 12053 input i;
12050 /*AUTOREG*/ 12054 /*AUTOREG*/
12051 // Beginning of automatic regs (for this module's undeclared outputs) 12055 // Beginning of automatic regs
12052 reg o; 12056 reg o;
12053 // End of automatics 12057 // End of automatics
12054 always o = i; 12058 always o = i;
12055 endmodule" 12059 endmodule"
12056 (save-excursion 12060 (save-excursion
12057 ;; Point must be at insertion point. 12061 ;; Point must be at insertion point.
12058 (let* ((indent-pt (current-indentation)) 12062 (let* ((indent-pt (current-indentation))
@@ -12093,30 +12097,27 @@ Limitations:
12093 12097
12094An example (see `verilog-auto-inst' for what else is going on here): 12098An example (see `verilog-auto-inst' for what else is going on here):
12095 12099
12096 module ExampRegInput (o,i); 12100 module InstModule (input i);
12097 output o; 12101 endmodule
12098 input i; 12102
12099 /*AUTOREGINPUT*/ 12103 module ExampRegInput ();
12104 /*AUTOREGINPUT*/
12100 InstModule instName 12105 InstModule instName
12101 (/*AUTOINST*/); 12106 (/*AUTOINST*/);
12102 endmodule 12107 endmodule
12103 12108
12104Typing \\[verilog-auto] will make this into: 12109Typing \\[verilog-auto] will make this into:
12105 12110
12106 module ExampRegInput (o,i); 12111 module ExampRegInput ();
12107 output o; 12112 /*AUTOREGINPUT*/
12108 input i; 12113 // Beginning of automatic reg inputs
12109 /*AUTOREGINPUT*/ 12114 reg i; // To instName of InstModule.v
12110 // Beginning of automatic reg inputs (for undeclared ... 12115 // End of automatics
12111 reg [31:0] iv; // From inst of inst.v 12116 InstModule instName
12112 // End of automatics
12113 InstModule instName
12114 (/*AUTOINST*/ 12117 (/*AUTOINST*/
12115 // Outputs 12118 // Inputs
12116 .o (o[31:0]), 12119 .i (i));
12117 // Inputs 12120 endmodule"
12118 .iv (iv));
12119 endmodule"
12120 (save-excursion 12121 (save-excursion
12121 ;; Point must be at insertion point. 12122 ;; Point must be at insertion point.
12122 (let* ((indent-pt (current-indentation)) 12123 (let* ((indent-pt (current-indentation))
@@ -12183,31 +12184,29 @@ Limitations:
12183 12184
12184An example (see `verilog-auto-inst' for what else is going on here): 12185An example (see `verilog-auto-inst' for what else is going on here):
12185 12186
12186 module ExampWire (o,i); 12187 module ExampWire (i);
12187 output o; 12188 input i;
12188 input i; 12189 /*AUTOWIRE*/
12189 /*AUTOWIRE*/
12190 InstModule instName 12190 InstModule instName
12191 (/*AUTOINST*/); 12191 (/*AUTOINST*/);
12192 endmodule 12192 endmodule
12193 12193
12194Typing \\[verilog-auto] will make this into: 12194Typing \\[verilog-auto] will make this into:
12195 12195
12196 module ExampWire (o,i); 12196 module ExampWire (i);
12197 output o; 12197 input i;
12198 input i; 12198 /*AUTOWIRE*/
12199 /*AUTOWIRE*/ 12199 // Beginning of automatic wires
12200 // Beginning of automatic wires 12200 wire [31:0] o; // From instName of InstModule.v
12201 wire [31:0] ov; // From inst of inst.v 12201 // End of automatics
12202 // End of automatics 12202 InstModule instName
12203 InstModule instName 12203 (/*AUTOINST*/
12204 (/*AUTOINST*/ 12204 // Outputs
12205 // Outputs 12205 .o (o[31:0]),
12206 .ov (ov[31:0]), 12206 // Inputs
12207 // Inputs 12207 .i (i));
12208 .i (i)); 12208 wire o = | ov;
12209 wire o = | ov; 12209 endmodule"
12210 endmodule"
12211 (save-excursion 12210 (save-excursion
12212 ;; Point must be at insertion point. 12211 ;; Point must be at insertion point.
12213 (let* ((indent-pt (current-indentation)) 12212 (let* ((indent-pt (current-indentation))
@@ -12254,28 +12253,29 @@ Limitations:
12254 12253
12255An example (see `verilog-auto-inst' for what else is going on here): 12254An example (see `verilog-auto-inst' for what else is going on here):
12256 12255
12257 module ExampOutput (ov,i); 12256 module InstModule (output o);
12258 input i; 12257 endmodule
12259 /*AUTOOUTPUT*/ 12258
12260 InstModule instName 12259 module ExampOutput
12261 (/*AUTOINST*/); 12260 (/*AUTOOUTPUT*/
12262 endmodule 12261 );
12262 InstModule instName
12263 (/*AUTOINST*/);
12264 endmodule
12263 12265
12264Typing \\[verilog-auto] will make this into: 12266Typing \\[verilog-auto] will make this into:
12265 12267
12266 module ExampOutput (ov,i); 12268 module ExampOutput
12267 input i; 12269 (/*AUTOOUTPUT*/
12268 /*AUTOOUTPUT*/ 12270 // Beginning of automatic outputs
12269 // Beginning of automatic outputs (from unused autoinst outputs) 12271 output o // From instName of InstModule.v
12270 output [31:0] ov; // From inst of inst.v 12272 // End of automatics
12271 // End of automatics 12273 );
12272 InstModule instName 12274 InstModule instName
12273 (/*AUTOINST*/ 12275 (/*AUTOINST*/
12274 // Outputs 12276 // Outputs
12275 .ov (ov[31:0]), 12277 .o (o));
12276 // Inputs 12278 endmodule
12277 .i (i));
12278 endmodule
12279 12279
12280You may also provide an optional regular expression, in which case only 12280You may also provide an optional regular expression, in which case only
12281signals matching the regular expression will be included. For example the 12281signals matching the regular expression will be included. For example the
@@ -12320,35 +12320,36 @@ won't optimize away the outputs.
12320 12320
12321An example: 12321An example:
12322 12322
12323 module ExampOutputEvery (o,i,tempa,tempb); 12323 module ExampOutputEvery (o,i,tempa,tempb);
12324 output o; 12324 output o;
12325 input i; 12325 input i;
12326 /*AUTOOUTPUTEVERY*/ 12326 /*AUTOOUTPUTEVERY*/
12327 wire tempa = i; 12327 wire tempa = i;
12328 wire tempb = tempa; 12328 wire tempb = tempa;
12329 wire o = tempb; 12329 wire o = tempb;
12330 endmodule 12330 endmodule
12331 12331
12332Typing \\[verilog-auto] will make this into: 12332Typing \\[verilog-auto] will make this into:
12333 12333
12334 module ExampOutputEvery (o,i,tempa,tempb); 12334 module ExampOutputEvery (
12335 output o; 12335 /*AUTOOUTPUTEVERY*/
12336 input i; 12336 // Beginning of automatic outputs (every signal)
12337 /*AUTOOUTPUTEVERY*/ 12337 output o,
12338 // Beginning of automatic outputs (every signal) 12338 output tempa,
12339 output tempb; 12339 output tempb,
12340 output tempa; 12340 // End of automatics
12341 // End of automatics 12341 input i
12342 wire tempa = i; 12342 );
12343 wire tempb = tempa; 12343 wire tempa = i;
12344 wire o = tempb; 12344 wire tempb = tempa;
12345 endmodule 12345 wire o = tempb;
12346 endmodule
12346 12347
12347You may also provide an optional regular expression, in which case only 12348You may also provide an optional regular expression, in which case only
12348signals matching the regular expression will be included. For example the 12349signals matching the regular expression will be included. For example the
12349same expansion will result from only extracting outputs starting with ov: 12350same expansion will result from only extracting outputs starting with ov:
12350 12351
12351 /*AUTOOUTPUTEVERY(\"^ov\")*/" 12352 /*AUTOOUTPUTEVERY(\"^ov\")*/"
12352 (save-excursion 12353 (save-excursion
12353 ;;Point must be at insertion point 12354 ;;Point must be at insertion point
12354 (let* ((indent-pt (current-indentation)) 12355 (let* ((indent-pt (current-indentation))
@@ -12398,28 +12399,29 @@ Limitations:
12398 12399
12399An example (see `verilog-auto-inst' for what else is going on here): 12400An example (see `verilog-auto-inst' for what else is going on here):
12400 12401
12401 module ExampInput (ov,i); 12402 module InstModule (input i);
12402 output [31:0] ov; 12403 endmodule
12403 /*AUTOINPUT*/ 12404
12404 InstModule instName 12405 module ExampInput (
12405 (/*AUTOINST*/); 12406 /*AUTOINPUT*/
12406 endmodule 12407 );
12408 InstModule instName
12409 (/*AUTOINST*/);
12410 endmodule
12407 12411
12408Typing \\[verilog-auto] will make this into: 12412Typing \\[verilog-auto] will make this into:
12409 12413
12410 module ExampInput (ov,i); 12414 module ExampInput (
12411 output [31:0] ov; 12415 /*AUTOINPUT*/
12412 /*AUTOINPUT*/ 12416 // Beginning of automatic inputs (from unused autoinst inputs)
12413 // Beginning of automatic inputs (from unused autoinst inputs) 12417 input i // To instName of InstModule.v
12414 input i; // From inst of inst.v 12418 // End of automatics
12415 // End of automatics 12419 );
12416 InstModule instName 12420 InstModule instName
12417 (/*AUTOINST*/ 12421 (/*AUTOINST*/
12418 // Outputs 12422 // Inputs
12419 .ov (ov[31:0]), 12423 .i (i));
12420 // Inputs 12424 endmodule
12421 .i (i));
12422 endmodule
12423 12425
12424You may also provide an optional regular expression, in which case only 12426You may also provide an optional regular expression, in which case only
12425signals matching the regular expression will be included. For example the 12427signals matching the regular expression will be included. For example the
@@ -12481,34 +12483,35 @@ Limitations:
12481 12483
12482An example (see `verilog-auto-inst' for what else is going on here): 12484An example (see `verilog-auto-inst' for what else is going on here):
12483 12485
12484 module ExampInout (ov,i); 12486 module InstModule (inout io);
12485 input i; 12487 endmodule
12486 /*AUTOINOUT*/ 12488
12487 InstModule instName 12489 module ExampInout (
12488 (/*AUTOINST*/); 12490 /*AUTOINOUT*/
12489 endmodule 12491 );
12492 InstModule instName
12493 (/*AUTOINST*/);
12494 endmodule
12490 12495
12491Typing \\[verilog-auto] will make this into: 12496Typing \\[verilog-auto] will make this into:
12492 12497
12493 module ExampInout (ov,i); 12498 module ExampInout (
12494 input i; 12499 /*AUTOINOUT*/
12495 /*AUTOINOUT*/ 12500 // Beginning of automatic inouts
12496 // Beginning of automatic inouts (from unused autoinst inouts) 12501 inout io // To/From instName of InstModule.v
12497 inout [31:0] ov; // From inst of inst.v 12502 // End of automatics
12498 // End of automatics 12503 );
12499 InstModule instName 12504 InstModule instName
12500 (/*AUTOINST*/ 12505 (/*AUTOINST*/
12501 // Inouts 12506 // Inouts
12502 .ov (ov[31:0]), 12507 .io (io));
12503 // Inputs 12508 endmodule
12504 .i (i));
12505 endmodule
12506 12509
12507You may also provide an optional regular expression, in which case only 12510You may also provide an optional regular expression, in which case only
12508signals matching the regular expression will be included. For example the 12511signals matching the regular expression will be included. For example the
12509same expansion will result from only extracting inouts starting with i: 12512same expansion will result from only extracting inouts starting with i:
12510 12513
12511 /*AUTOINOUT(\"^i\")*/" 12514 /*AUTOINOUT(\"^i\")*/"
12512 (save-excursion 12515 (save-excursion
12513 ;; Point must be at insertion point. 12516 ;; Point must be at insertion point.
12514 (let* ((indent-pt (current-indentation)) 12517 (let* ((indent-pt (current-indentation))
@@ -12566,32 +12569,32 @@ Limitations:
12566 12569
12567An example: 12570An example:
12568 12571
12569 module ExampShell (/*AUTOARG*/); 12572 module ExampMain
12570 /*AUTOINOUTMODULE(\"ExampMain\")*/ 12573 (input i,
12571 endmodule 12574 output o,
12575 inout io);
12576 endmodule
12572 12577
12573 module ExampMain (i,o,io); 12578 module ExampShell (/*AUTOARG*/);
12574 input i; 12579 /*AUTOINOUTMODULE(\"ExampMain\")*/
12575 output o;
12576 inout io;
12577 endmodule 12580 endmodule
12578 12581
12579Typing \\[verilog-auto] will make this into: 12582Typing \\[verilog-auto] will make this into:
12580 12583
12581 module ExampShell (/*AUTOARG*/i,o,io); 12584 module ExampShell (/*AUTOARG*/o, io, o);
12582 /*AUTOINOUTMODULE(\"ExampMain\")*/ 12585 /*AUTOINOUTMODULE(\"ExampMain\")*/
12583 // Beginning of automatic in/out/inouts (from specific module) 12586 // Beginning of automatic in/out/inouts
12584 output o; 12587 output o;
12585 inout io; 12588 inout io;
12586 input i; 12589 input i;
12587 // End of automatics 12590 // End of automatics
12588 endmodule 12591 endmodule
12589 12592
12590You may also provide an optional regular expression, in which case only 12593You may also provide an optional regular expression, in which case only
12591signals matching the regular expression will be included. For example the 12594signals matching the regular expression will be included. For example the
12592same expansion will result from only extracting signals starting with i: 12595same expansion will result from only extracting signals starting with i:
12593 12596
12594 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/ 12597 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12595 12598
12596You may also provide an optional third argument regular 12599You may also provide an optional third argument regular
12597expression, in which case only signals which have that pin 12600expression, in which case only signals which have that pin
@@ -12605,7 +12608,7 @@ probably want to skip spaces in your regexp.
12605For example, the below will result in matching the output \"o\" 12608For example, the below will result in matching the output \"o\"
12606against the previous example's module: 12609against the previous example's module:
12607 12610
12608 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/ 12611 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
12609 12612
12610You may also provide an optional fourth argument regular 12613You may also provide an optional fourth argument regular
12611expression, which if not \"\" only signals which do NOT match 12614expression, which if not \"\" only signals which do NOT match
@@ -12704,32 +12707,32 @@ Limitations:
12704 12707
12705An example: 12708An example:
12706 12709
12707 module ExampShell (/*AUTOARG*/); 12710 module ExampMain
12708 /*AUTOINOUTCOMP(\"ExampMain\")*/ 12711 (input i,
12709 endmodule 12712 output o,
12713 inout io);
12714 endmodule
12710 12715
12711 module ExampMain (i,o,io); 12716 module ExampBench (/*AUTOARG*/);
12712 input i; 12717 /*AUTOINOUTCOMP(\"ExampMain\")*/
12713 output o;
12714 inout io;
12715 endmodule 12718 endmodule
12716 12719
12717Typing \\[verilog-auto] will make this into: 12720Typing \\[verilog-auto] will make this into:
12718 12721
12719 module ExampShell (/*AUTOARG*/i,o,io); 12722 module ExampShell (/*AUTOARG*/i, io, o);
12720 /*AUTOINOUTCOMP(\"ExampMain\")*/ 12723 /*AUTOINOUTCOMP(\"ExampMain\")*/
12721 // Beginning of automatic in/out/inouts (from specific module) 12724 // Beginning of automatic in/out/inouts
12722 output i; 12725 output i;
12723 inout io; 12726 inout io;
12724 input o; 12727 input o;
12725 // End of automatics 12728 // End of automatics
12726 endmodule 12729 endmodule
12727 12730
12728You may also provide an optional regular expression, in which case only 12731You may also provide an optional regular expression, in which case only
12729signals matching the regular expression will be included. For example the 12732signals matching the regular expression will be included. For example the
12730same expansion will result from only extracting signals starting with i: 12733same expansion will result from only extracting signals starting with i:
12731 12734
12732 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/ 12735 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
12733 12736
12734You may also provide an optional third argument regular 12737You may also provide an optional third argument regular
12735expression, in which case only signals which have that pin 12738expression, in which case only signals which have that pin
@@ -12743,7 +12746,7 @@ probably want to skip spaces in your regexp.
12743For example, the below will result in matching the output \"o\" 12746For example, the below will result in matching the output \"o\"
12744against the previous example's module: 12747against the previous example's module:
12745 12748
12746 /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/ 12749 /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
12747 12750
12748You may also provide an optional fourth argument regular 12751You may also provide an optional fourth argument regular
12749expression, which if not \"\" only signals which do NOT match 12752expression, which if not \"\" only signals which do NOT match
@@ -12774,32 +12777,32 @@ Limitations:
12774 12777
12775An example: 12778An example:
12776 12779
12777 module ExampShell (/*AUTOARG*/); 12780 module ExampMain
12778 /*AUTOINOUTIN(\"ExampMain\")*/ 12781 (input i,
12779 endmodule 12782 output o,
12783 inout io);
12784 endmodule
12780 12785
12781 module ExampMain (i,o,io); 12786 module ExampInoutIn (/*AUTOARG*/);
12782 input i; 12787 /*AUTOINOUTIN(\"ExampMain\")*/
12783 output o;
12784 inout io;
12785 endmodule 12788 endmodule
12786 12789
12787Typing \\[verilog-auto] will make this into: 12790Typing \\[verilog-auto] will make this into:
12788 12791
12789 module ExampShell (/*AUTOARG*/i,o,io); 12792 module ExampInoutIn (/*AUTOARG*/i, io, o);
12790 /*AUTOINOUTIN(\"ExampMain\")*/ 12793 /*AUTOINOUTIN(\"ExampMain\")*/
12791 // Beginning of automatic in/out/inouts (from specific module) 12794 // Beginning of automatic in/out/inouts
12792 input i; 12795 input i;
12793 input io; 12796 input io;
12794 input o; 12797 input o;
12795 // End of automatics 12798 // End of automatics
12796 endmodule 12799 endmodule
12797 12800
12798You may also provide an optional regular expression, in which case only 12801You may also provide an optional regular expression, in which case only
12799signals matching the regular expression will be included. For example the 12802signals matching the regular expression will be included. For example the
12800same expansion will result from only extracting signals starting with i: 12803same expansion will result from only extracting signals starting with i:
12801 12804
12802 /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/" 12805 /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
12803 (verilog-auto-inout-module nil t)) 12806 (verilog-auto-inout-module nil t))
12804 12807
12805(defun verilog-auto-inout-param () 12808(defun verilog-auto-inout-param ()
@@ -12823,28 +12826,28 @@ Limitations:
12823 12826
12824An example: 12827An example:
12825 12828
12826 module ExampShell (); 12829 module ExampMain ();
12827 /*AUTOINOUTPARAM(\"ExampMain\")*/
12828 endmodule
12829
12830 module ExampMain ();
12831 parameter PARAM = 22; 12830 parameter PARAM = 22;
12832 endmodule 12831 endmodule
12833 12832
12833 module ExampInoutParam ();
12834 /*AUTOINOUTPARAM(\"ExampMain\")*/
12835 endmodule
12836
12834Typing \\[verilog-auto] will make this into: 12837Typing \\[verilog-auto] will make this into:
12835 12838
12836 module ExampShell (/*AUTOARG*/i,o,io); 12839 module ExampInoutParam ();
12837 /*AUTOINOUTPARAM(\"ExampMain\")*/ 12840 /*AUTOINOUTPARAM(\"ExampMain\")*/
12838 // Beginning of automatic parameters (from specific module) 12841 // Beginning of automatic parameters (from specific module)
12839 parameter PARAM; 12842 parameter PARAM;
12840 // End of automatics 12843 // End of automatics
12841 endmodule 12844 endmodule
12842 12845
12843You may also provide an optional regular expression, in which case only 12846You may also provide an optional regular expression, in which case only
12844parameters matching the regular expression will be included. For example the 12847parameters matching the regular expression will be included. For example the
12845same expansion will result from only extracting parameters starting with i: 12848same expansion will result from only extracting parameters starting with i:
12846 12849
12847 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/" 12850 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
12848 (save-excursion 12851 (save-excursion
12849 (let* ((params (verilog-read-auto-params 1 2)) 12852 (let* ((params (verilog-read-auto-params 1 2))
12850 (submod (nth 0 params)) 12853 (submod (nth 0 params))
@@ -12897,39 +12900,34 @@ the same name.
12897 12900
12898An example: 12901An example:
12899 12902
12900 interface ExampIf 12903 interface ExampIf
12901 ( input logic clk ); 12904 ( input logic clk );
12902 logic req_val; 12905 logic req_val;
12903 logic [7:0] req_dat; 12906 logic [7:0] req_dat;
12904 clocking mon_clkblk @(posedge clk); 12907 clocking mon_clkblk @(posedge clk);
12905 input req_val; 12908 input req_val;
12906 input req_dat; 12909 input req_dat;
12907 endclocking 12910 endclocking
12908 modport mp(clocking mon_clkblk); 12911 modport mp(clocking mon_clkblk);
12909 endinterface 12912 endinterface
12910 12913
12911 module ExampMain 12914 module ExampMain
12912 ( input clk, 12915 ( input clk,
12913 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/ 12916 /*AUTOINOUTMODPORT(\"ExampIf\", \"mp\")*/
12914 // Beginning of automatic in/out/inouts (from modport) 12917 );
12915 input [7:0] req_dat, 12918 endmodule
12916 input req_val
12917 // End of automatics
12918 );
12919 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12920 endmodule
12921 12919
12922Typing \\[verilog-auto] will make this into: 12920Typing \\[verilog-auto] will make this into:
12923 12921
12924 ... 12922 module ExampMain
12925 module ExampMain 12923 ( input clk,
12926 ( input clk, 12924 /*AUTOINOUTMODPORT(\"ExampIf\", \"mp\")*/
12927 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/ 12925 // Beginning of automatic in/out/inouts (from modport)
12928 // Beginning of automatic in/out/inouts (from modport) 12926 input req_val,
12929 input req_dat, 12927 input [7:0] req_dat
12930 input req_val 12928 // End of automatics
12931 // End of automatics 12929 );
12932 ); 12930 endmodule
12933 12931
12934If the modport is part of a UVM monitor/driver class, this 12932If the modport is part of a UVM monitor/driver class, this
12935creates a wrapper module that may be used to instantiate the 12933creates a wrapper module that may be used to instantiate the
@@ -13005,35 +13003,36 @@ it during `verilog-auto-inst' but does not insert any text.
13005 13003
13006An example: 13004An example:
13007 13005
13008 module ExampInsertLisp; 13006 module ExampInsertLisp;
13009 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/ 13007 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
13010 endmodule 13008 endmodule
13011 13009
13012 // For this example we declare the function in the 13010 // For this example we declare the function in the
13013 // module's file itself. Often you'd define it instead 13011 // module's file itself. Often you'd define it instead
13014 // in a site-start.el or init file. 13012 // in a site-start.el or init file.
13015 /* 13013 /*
13016 Local Variables: 13014 Local Variables:
13017 eval: 13015 eval:
13018 (defun my-verilog-insert-hello (who) 13016 (defun my-verilog-insert-hello (who)
13019 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\"))) 13017 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
13020 End: 13018 End:
13021 */ 13019 */
13022 13020
13023Typing \\[verilog-auto] will call my-verilog-insert-hello and 13021Typing \\[verilog-auto] will call my-verilog-insert-hello and
13024expand the above into: 13022expand the above into:
13025 13023
13026 // Beginning of automatic insert lisp 13024 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
13027 initial $write(\"hello world\"); 13025 // Beginning of automatic insert lisp
13028 // End of automatics 13026 initial $write(\"hello world\");
13027 // End of automatics
13029 13028
13030You can also call an external program and insert the returned 13029You can also call an external program and insert the returned
13031text: 13030text:
13032 13031
13033 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/ 13032 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
13034 // Beginning of automatic insert lisp 13033 // Beginning of automatic insert lisp
13035 //hello 13034 //hello
13036 // End of automatics" 13035 // End of automatics"
13037 (save-excursion 13036 (save-excursion
13038 ;; Point is at end of /*AUTO...*/ 13037 ;; Point is at end of /*AUTO...*/
13039 (let* ((indent-pt (current-indentation)) 13038 (let* ((indent-pt (current-indentation))
@@ -13119,27 +13118,27 @@ OOps!
13119 13118
13120An example: 13119An example:
13121 13120
13122 always @ (/*AS*/) begin 13121 always @ (/*AS*/) begin
13123 /* AUTO_CONSTANT (\\=`constant) */ 13122 /*AUTO_CONSTANT (\\=`constant) */
13124 outin = ina | inb | \\=`constant; 13123 outin = ina | inb | \\=`constant;
13125 out = outin; 13124 out = outin;
13126 end 13125 end
13127 13126
13128Typing \\[verilog-auto] will make this into: 13127Typing \\[verilog-auto] will make this into:
13129 13128
13130 always @ (/*AS*/ina or inb) begin 13129 always @ (/*AS*/ina or inb) begin
13131 /* AUTO_CONSTANT (\\=`constant) */ 13130 /*AUTO_CONSTANT (\\=`constant) */
13132 outin = ina | inb | \\=`constant; 13131 outin = ina | inb | \\=`constant;
13133 out = outin; 13132 out = outin;
13134 end 13133 end
13135 13134
13136Note in Verilog 2001, you can often get the same result from the new @* 13135Note in Verilog 2001, you can often get the same result from the new @*
13137operator. (This was added to the language in part due to AUTOSENSE!) 13136operator. (This was added to the language in part due to AUTOSENSE!)
13138 13137
13139 always @* begin 13138 always @* begin
13140 outin = ina | inb | \\=`constant; 13139 outin = ina | inb | \\=`constant;
13141 out = outin; 13140 out = outin;
13142 end" 13141 end"
13143 (save-excursion 13142 (save-excursion
13144 ;; Find beginning 13143 ;; Find beginning
13145 (let* ((start-pt (save-excursion 13144 (let* ((start-pt (save-excursion
@@ -13220,35 +13219,30 @@ signals manually (or put them into a \"\\=`ifdef NEVER signal<=\\=`0;
13220 13219
13221An example: 13220An example:
13222 13221
13223 always @(posedge clk or negedge reset_l) begin 13222 module ExampReset ();
13224 if (!reset_l) begin 13223 always @(posedge clk or negedge reset_l) begin
13225 c <= 1; 13224 if (!reset_l) begin
13226 /*AUTORESET*/ 13225 c <= 1;
13227 end 13226 /*AUTORESET*/
13228 else begin 13227 end
13229 a <= in_a; 13228 else begin
13230 b <= in_b; 13229 a <= in_a;
13231 c <= in_c; 13230 b <= in_b;
13232 end 13231 c <= in_c;
13233 end 13232 end
13233 end
13234 endmodule
13234 13235
13235Typing \\[verilog-auto] will make this into: 13236Typing \\[verilog-auto] will make this into:
13236 13237
13237 always @(posedge core_clk or negedge reset_l) begin 13238 ...
13238 if (!reset_l) begin 13239 c <= 1;
13239 c <= 1; 13240 /*AUTORESET*/
13240 /*AUTORESET*/ 13241 // Beginning of autoreset for uninitialized flops
13241 // Beginning of autoreset for uninitialized flops 13242 a <= 1'h0;
13242 a <= 0; 13243 b <= 1'h0;
13243 b = 0; // if `verilog-auto-reset-blocking-in-non' true 13244 // End of automatics
13244 // End of automatics 13245 ..."
13245 end
13246 else begin
13247 a <= in_a;
13248 b = in_b;
13249 c <= in_c;
13250 end
13251 end"
13252 13246
13253 (interactive) 13247 (interactive)
13254 (save-excursion 13248 (save-excursion
@@ -13324,32 +13318,32 @@ value's width is generated.
13324 13318
13325An example of making a stub for another module: 13319An example of making a stub for another module:
13326 13320
13327 module ExampStub (/*AUTOINST*/); 13321 module ExampMain
13328 /*AUTOINOUTPARAM(\"Foo\")*/ 13322 #(parameter P)
13329 /*AUTOINOUTMODULE(\"Foo\")*/ 13323 (input i, output o, inout io);
13330 /*AUTOTIEOFF*/ 13324 endmodule
13331 // verilator lint_off UNUSED
13332 wire _unused_ok = &{1\\='b0,
13333 /*AUTOUNUSED*/
13334 1\\='b0};
13335 // verilator lint_on UNUSED
13336 endmodule
13337 13325
13338Typing \\[verilog-auto] will make this into: 13326 module ExampStub (/*AUTOARG*/);
13327 /*AUTOINOUTPARAM(\"ExampMain\")*/
13328 /*AUTOINOUTMODULE(\"ExampMain\")*/
13339 13329
13340 module ExampStub (/*AUTOINST*/...); 13330 /*AUTOTIEOFF*/
13341 /*AUTOINOUTPARAM(\"Foo\")*/ 13331
13342 /*AUTOINOUTMODULE(\"Foo\")*/ 13332 // verilator lint_off UNUSED
13343 // Beginning of autotieoff 13333 wire _unused_ok = &{1\\='b0,
13344 output [2:0] foo; 13334 /*AUTOUNUSED*/
13345 // End of automatics 13335 1\\='b0};
13336 // verilator lint_on UNUSED
13337 endmodule
13338
13339Typing \\[verilog-auto] will make this into:
13346 13340
13341 ...
13347 /*AUTOTIEOFF*/ 13342 /*AUTOTIEOFF*/
13348 // Beginning of autotieoff 13343 // Beginning of automatic tieoffs
13349 wire [2:0] foo = 3\\='b0; 13344 wire [2:0] o = 3\\='b0;
13350 // End of automatics 13345 // End of automatics
13351 ... 13346 ..."
13352 endmodule"
13353 (interactive) 13347 (interactive)
13354 (save-excursion 13348 (save-excursion
13355 ;; Find beginning 13349 ;; Find beginning
@@ -13402,24 +13396,24 @@ Limitations:
13402 13396
13403An example: 13397An example:
13404 13398
13405 \\=`define XX_FOO 13399 \\=`define XX_FOO
13406 \\=`define M_BAR(x) 13400 \\=`define M_BAR(x)
13407 \\=`define M_BAZ 13401 \\=`define M_BAZ
13408 ... 13402 ...
13409 \\=`ifdef NEVER 13403 \\=`ifdef NEVER
13410 \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ 13404 \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
13411 \\=`endif 13405 \\=`endif
13412 ... 13406 ...
13413 /*AUTOUNDEF*/ 13407 /*AUTOUNDEF*/
13414 13408
13415Typing \\[verilog-auto] will make this into: 13409Typing \\[verilog-auto] will make this into:
13416 13410
13417 ... 13411 ...
13418 /*AUTOUNDEF*/ 13412 /*AUTOUNDEF*/
13419 // Beginning of automatic undefs 13413 // Beginning of automatic undefs
13420 \\=`undef XX_FOO 13414 \\=`undef M_BAR
13421 \\=`undef M_BAR 13415 \\=`undef XX_FOO
13422 // End of automatics 13416 // End of automatics
13423 13417
13424You may also provide an optional regular expression, in which case only 13418You may also provide an optional regular expression, in which case only
13425defines the regular expression will be undefed." 13419defines the regular expression will be undefed."
@@ -13482,31 +13476,36 @@ You can add signals you do not want included in AUTOUNUSED with
13482 13476
13483An example of making a stub for another module: 13477An example of making a stub for another module:
13484 13478
13485 module ExampStub (/*AUTOINST*/); 13479 module ExampMain
13486 /*AUTOINOUTPARAM(\"Examp\")*/ 13480 (input unused_input_a, input unused_input_b);
13487 /*AUTOINOUTMODULE(\"Examp\")*/ 13481 endmodule
13488 /*AUTOTIEOFF*/ 13482
13489 // verilator lint_off UNUSED 13483 module ExampStub2 (/*AUTOARG*/);
13490 wire _unused_ok = &{1\\='b0, 13484 /*AUTOINOUTPARAM(\"ExampMain\")*/
13491 /*AUTOUNUSED*/ 13485 /*AUTOINOUTMODULE(\"ExampMain\")*/
13492 1\\='b0}; 13486
13493 // verilator lint_on UNUSED 13487 /*AUTOTIEOFF*/
13494 endmodule 13488
13489 // verilator lint_off UNUSED
13490 wire _unused_ok = &{1\\='b0,
13491 /*AUTOUNUSED*/
13492 1\\='b0};
13493 // verilator lint_on UNUSED
13494 endmodule
13495 13495
13496Typing \\[verilog-auto] will make this into: 13496Typing \\[verilog-auto] will make this into:
13497 13497
13498 ... 13498 ...
13499 // verilator lint_off UNUSED 13499 // verilator lint_off UNUSED
13500 wire _unused_ok = &{1\\='b0, 13500 wire _unused_ok = &{1\\='b0,
13501 /*AUTOUNUSED*/ 13501 /*AUTOUNUSED*/
13502 // Beginning of automatics 13502 // Beginning of automatics
13503 unused_input_a, 13503 unused_input_a,
13504 unused_input_b, 13504 unused_input_b
13505 unused_input_c, 13505 // End of automatics
13506 // End of automatics 13506 1\\='b0};
13507 1\\='b0}; 13507 // verilator lint_on UNUSED
13508 // verilator lint_on UNUSED 13508 endmodule"
13509 endmodule"
13510 (interactive) 13509 (interactive)
13511 (save-excursion 13510 (save-excursion
13512 ;; Find beginning 13511 ;; Find beginning
@@ -13577,35 +13576,34 @@ Finally, an AUTOASCIIENUM command is used.
13577 13576
13578An example: 13577An example:
13579 13578
13580 //== State enumeration 13579 //== State enumeration
13581 parameter [2:0] // auto enum state_info 13580 parameter [2:0] // auto enum state_info
13582 SM_IDLE = 3\\='b000, 13581 SM_IDLE = 3\\='b000,
13583 SM_SEND = 3\\='b001, 13582 SM_SEND = 3\\='b001,
13584 SM_WAIT1 = 3\\='b010; 13583 SM_WAIT1 = 3\\='b010;
13585 //== State variables 13584 //== State variables
13586 reg [2:0] /* auto enum state_info */ 13585 reg [2:0] /* auto enum state_info */
13587 state_r; /* auto state_vector state_r */ 13586 state_r; /* auto state_vector state_r */
13588 reg [2:0] /* auto enum state_info */ 13587 reg [2:0] /* auto enum state_info */
13589 state_e1; 13588 state_e1;
13590 13589
13591 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/ 13590 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13592 13591
13593Typing \\[verilog-auto] will make this into: 13592Typing \\[verilog-auto] will make this into:
13594 13593
13595 ... same front matter ... 13594 ...
13596 13595 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13597 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/ 13596 // Beginning of automatic ASCII enum decoding
13598 // Beginning of automatic ASCII enum decoding 13597 reg [39:0] state_ascii_r; // Decode of state_r
13599 reg [39:0] state_ascii_r; // Decode of state_r 13598 always @(state_r) begin
13600 always @(state_r) begin 13599 case ({state_r})
13601 case ({state_r}) 13600 SM_IDLE: state_ascii_r = \"idle \";
13602 SM_IDLE: state_ascii_r = \"idle \"; 13601 SM_SEND: state_ascii_r = \"send \";
13603 SM_SEND: state_ascii_r = \"send \"; 13602 SM_WAIT1: state_ascii_r = \"wait1\";
13604 SM_WAIT1: state_ascii_r = \"wait1\"; 13603 default: state_ascii_r = \"%Erro\";
13605 default: state_ascii_r = \"%Erro\"; 13604 endcase
13606 endcase 13605 end
13607 end 13606 // End of automatics"
13608 // End of automatics"
13609 (save-excursion 13607 (save-excursion
13610 (let* ((params (verilog-read-auto-params 2 4)) 13608 (let* ((params (verilog-read-auto-params 2 4))
13611 (undecode-name (nth 0 params)) 13609 (undecode-name (nth 0 params))
@@ -13776,12 +13774,13 @@ The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13776called before and after this function, respectively. 13774called before and after this function, respectively.
13777 13775
13778For example: 13776For example:
13779 module ModuleName (/*AUTOARG*/); 13777 module ExampModule (/*AUTOARG*/);
13780 /*AUTOINPUT*/ 13778 /*AUTOINPUT*/
13781 /*AUTOOUTPUT*/ 13779 /*AUTOOUTPUT*/
13782 /*AUTOWIRE*/ 13780 /*AUTOWIRE*/
13783 /*AUTOREG*/ 13781 /*AUTOREG*/
13784 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/); 13782 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13783 endmodule
13785 13784
13786You can also update the AUTOs from the shell using: 13785You can also update the AUTOs from the shell using:
13787 emacs --batch <filenames.v> -f verilog-batch-auto 13786 emacs --batch <filenames.v> -f verilog-batch-auto
generated by cgit v1.2.1 (git 2.18.0) at 2026-02-09 06:06:35 +0000