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| author | Miles Bader | 2008-02-01 04:44:30 +0000 |
|---|---|---|
| committer | Miles Bader | 2008-02-01 04:44:30 +0000 |
| commit | dd559368b0db67654f643320b1d84afdabe60e97 (patch) | |
| tree | b0e242d49f8e0f70c83c791b6ba34c34376ede2f | |
| parent | a9989764a4d54bf58381d5c3902e575bdf314245 (diff) | |
| parent | bf120ed1b9f1fa5a2422465e7ca825080b7b0c65 (diff) | |
| download | emacs-dd559368b0db67654f643320b1d84afdabe60e97.tar.gz emacs-dd559368b0db67654f643320b1d84afdabe60e97.zip | |
Merge from emacs--devo--0
Revision: emacs@sv.gnu.org/emacs--unicode--0--patch-330
| -rw-r--r-- | lisp/ChangeLog | 8 | ||||
| -rw-r--r-- | lisp/doc-view.el | 3 | ||||
| -rw-r--r-- | lisp/progmodes/verilog-mode.el | 46 | ||||
| -rw-r--r-- | src/ChangeLog | 4 | ||||
| -rw-r--r-- | src/xfaces.c | 2 |
5 files changed, 37 insertions, 26 deletions
diff --git a/lisp/ChangeLog b/lisp/ChangeLog index cf96534421b..dd061934b7c 100644 --- a/lisp/ChangeLog +++ b/lisp/ChangeLog | |||
| @@ -1,3 +1,11 @@ | |||
| 1 | 2008-02-01 Dan Nicolaescu <dann@ics.uci.edu> | ||
| 2 | |||
| 3 | * progmodes/verilog-mode.el (verilog-sk-prompt-msb) | ||
| 4 | (verilog-sk-module, verilog-sk-function, verilog-sk-begin) | ||
| 5 | (verilog-sk-if, verilog-sk-wire, verilog-sk-for) | ||
| 6 | (verilog-sk-state-machine): Quote all calls to | ||
| 7 | "auxiliary skeleton"s to prevent infloops. | ||
| 8 | |||
| 1 | 2008-02-01 Jason Rumney <jasonr@gnu.org> | 9 | 2008-02-01 Jason Rumney <jasonr@gnu.org> |
| 2 | 10 | ||
| 3 | * w32-fns.el: Partially revert 2007-11-10 change. | 11 | * w32-fns.el: Partially revert 2007-11-10 change. |
diff --git a/lisp/doc-view.el b/lisp/doc-view.el index aaa68bf6387..505c2311d7b 100644 --- a/lisp/doc-view.el +++ b/lisp/doc-view.el | |||
| @@ -943,7 +943,8 @@ If BACKWARD is non-nil, jump to the previous match." | |||
| 943 | (defun doc-view-mode () | 943 | (defun doc-view-mode () |
| 944 | "Major mode in DocView buffers. | 944 | "Major mode in DocView buffers. |
| 945 | You can use \\<doc-view-mode-map>\\[doc-view-toggle-display] to | 945 | You can use \\<doc-view-mode-map>\\[doc-view-toggle-display] to |
| 946 | toggle between displaying the document or editing it as text." | 946 | toggle between displaying the document or editing it as text. |
| 947 | \\{doc-view-mode-map}" | ||
| 947 | (interactive) | 948 | (interactive) |
| 948 | 949 | ||
| 949 | (let* ((prev-major-mode (if (eq major-mode 'doc-view-mode) | 950 | (let* ((prev-major-mode (if (eq major-mode 'doc-view-mode) |
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el index c177ca1b184..da91e36ca3d 100644 --- a/lisp/progmodes/verilog-mode.el +++ b/lisp/progmodes/verilog-mode.el | |||
| @@ -9539,7 +9539,7 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com." | |||
| 9539 | 9539 | ||
| 9540 | (define-skeleton verilog-sk-prompt-msb | 9540 | (define-skeleton verilog-sk-prompt-msb |
| 9541 | "Prompt for least significant bit specification." | 9541 | "Prompt for least significant bit specification." |
| 9542 | "msb:" str & ?: & (verilog-sk-prompt-lsb) | -1 ) | 9542 | "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 ) |
| 9543 | 9543 | ||
| 9544 | (define-skeleton verilog-sk-prompt-lsb | 9544 | (define-skeleton verilog-sk-prompt-lsb |
| 9545 | "Prompt for least significant bit specification." | 9545 | "Prompt for least significant bit specification." |
| @@ -9578,21 +9578,21 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com." | |||
| 9578 | (define-skeleton verilog-sk-module | 9578 | (define-skeleton verilog-sk-module |
| 9579 | "Insert a module definition." | 9579 | "Insert a module definition." |
| 9580 | () | 9580 | () |
| 9581 | > "module " (verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n | 9581 | > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n |
| 9582 | > _ \n | 9582 | > _ \n |
| 9583 | > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil)) | 9583 | > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil)) |
| 9584 | 9584 | ||
| 9585 | (define-skeleton verilog-sk-primitive | 9585 | (define-skeleton verilog-sk-primitive |
| 9586 | "Insert a task definition." | 9586 | "Insert a task definition." |
| 9587 | () | 9587 | () |
| 9588 | > "primitive " (verilog-sk-prompt-name) " ( " (verilog-sk-prompt-output) ("input:" ", " str ) " );"\n | 9588 | > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n |
| 9589 | > _ \n | 9589 | > _ \n |
| 9590 | > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil)) | 9590 | > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil)) |
| 9591 | 9591 | ||
| 9592 | (define-skeleton verilog-sk-task | 9592 | (define-skeleton verilog-sk-task |
| 9593 | "Insert a task definition." | 9593 | "Insert a task definition." |
| 9594 | () | 9594 | () |
| 9595 | > "task " (verilog-sk-prompt-name) & ?; \n | 9595 | > "task " '(verilog-sk-prompt-name) & ?; \n |
| 9596 | > _ \n | 9596 | > _ \n |
| 9597 | > "begin" \n | 9597 | > "begin" \n |
| 9598 | > \n | 9598 | > \n |
| @@ -9602,7 +9602,7 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com." | |||
| 9602 | (define-skeleton verilog-sk-function | 9602 | (define-skeleton verilog-sk-function |
| 9603 | "Insert a function definition." | 9603 | "Insert a function definition." |
| 9604 | () | 9604 | () |
| 9605 | > "function [" (verilog-sk-prompt-width) | -1 (verilog-sk-prompt-name) ?; \n | 9605 | > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n |
| 9606 | > _ \n | 9606 | > _ \n |
| 9607 | > "begin" \n | 9607 | > "begin" \n |
| 9608 | > \n | 9608 | > \n |
| @@ -9642,7 +9642,7 @@ for sensitivity list." | |||
| 9642 | (define-skeleton verilog-sk-begin | 9642 | (define-skeleton verilog-sk-begin |
| 9643 | "Insert begin end block. Uses the minibuffer to prompt for name" | 9643 | "Insert begin end block. Uses the minibuffer to prompt for name" |
| 9644 | () | 9644 | () |
| 9645 | > "begin" (verilog-sk-prompt-name) \n | 9645 | > "begin" '(verilog-sk-prompt-name) \n |
| 9646 | > _ \n | 9646 | > _ \n |
| 9647 | > (- verilog-indent-level-behavioral) "end" | 9647 | > (- verilog-indent-level-behavioral) "end" |
| 9648 | ) | 9648 | ) |
| @@ -9687,42 +9687,42 @@ and the case items." | |||
| 9687 | 9687 | ||
| 9688 | (define-skeleton verilog-sk-if | 9688 | (define-skeleton verilog-sk-if |
| 9689 | "Insert a skeleton if statement." | 9689 | "Insert a skeleton if statement." |
| 9690 | > "if (" (verilog-sk-prompt-condition) & ")" " begin" \n | 9690 | > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n |
| 9691 | > _ \n | 9691 | > _ \n |
| 9692 | > (- verilog-indent-level-behavioral) "end " \n ) | 9692 | > (- verilog-indent-level-behavioral) "end " \n ) |
| 9693 | 9693 | ||
| 9694 | (define-skeleton verilog-sk-else-if | 9694 | (define-skeleton verilog-sk-else-if |
| 9695 | "Insert a skeleton else if statement." | 9695 | "Insert a skeleton else if statement." |
| 9696 | > (verilog-indent-line) "else if (" | 9696 | > (verilog-indent-line) "else if (" |
| 9697 | (progn (setq verilog-sk-p (point)) nil) (verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n | 9697 | (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n |
| 9698 | > _ \n | 9698 | > _ \n |
| 9699 | > "end" (progn (electric-verilog-terminate-line) nil)) | 9699 | > "end" (progn (electric-verilog-terminate-line) nil)) |
| 9700 | 9700 | ||
| 9701 | (define-skeleton verilog-sk-datadef | 9701 | (define-skeleton verilog-sk-datadef |
| 9702 | "Common routine to get data definition" | 9702 | "Common routine to get data definition" |
| 9703 | () | 9703 | () |
| 9704 | (verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n) | 9704 | '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n) |
| 9705 | 9705 | ||
| 9706 | (define-skeleton verilog-sk-input | 9706 | (define-skeleton verilog-sk-input |
| 9707 | "Insert an input definition." | 9707 | "Insert an input definition." |
| 9708 | () | 9708 | () |
| 9709 | > "input [" (verilog-sk-datadef)) | 9709 | > "input [" '(verilog-sk-datadef)) |
| 9710 | 9710 | ||
| 9711 | (define-skeleton verilog-sk-output | 9711 | (define-skeleton verilog-sk-output |
| 9712 | "Insert an output definition." | 9712 | "Insert an output definition." |
| 9713 | () | 9713 | () |
| 9714 | > "output [" (verilog-sk-datadef)) | 9714 | > "output [" '(verilog-sk-datadef)) |
| 9715 | 9715 | ||
| 9716 | (define-skeleton verilog-sk-inout | 9716 | (define-skeleton verilog-sk-inout |
| 9717 | "Insert an inout definition." | 9717 | "Insert an inout definition." |
| 9718 | () | 9718 | () |
| 9719 | > "inout [" (verilog-sk-datadef)) | 9719 | > "inout [" '(verilog-sk-datadef)) |
| 9720 | 9720 | ||
| 9721 | (defvar verilog-sk-signal nil) | 9721 | (defvar verilog-sk-signal nil) |
| 9722 | (define-skeleton verilog-sk-def-reg | 9722 | (define-skeleton verilog-sk-def-reg |
| 9723 | "Insert a reg definition." | 9723 | "Insert a reg definition." |
| 9724 | () | 9724 | () |
| 9725 | > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) ) | 9725 | > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) ) |
| 9726 | 9726 | ||
| 9727 | (defun verilog-sk-define-signal () | 9727 | (defun verilog-sk-define-signal () |
| 9728 | "Insert a definition of signal under point at top of module." | 9728 | "Insert a definition of signal under point at top of module." |
| @@ -9748,29 +9748,29 @@ and the case items." | |||
| 9748 | (define-skeleton verilog-sk-wire | 9748 | (define-skeleton verilog-sk-wire |
| 9749 | "Insert a wire definition." | 9749 | "Insert a wire definition." |
| 9750 | () | 9750 | () |
| 9751 | > "wire [" (verilog-sk-datadef)) | 9751 | > "wire [" '(verilog-sk-datadef)) |
| 9752 | 9752 | ||
| 9753 | (define-skeleton verilog-sk-reg | 9753 | (define-skeleton verilog-sk-reg |
| 9754 | "Insert a reg definition." | 9754 | "Insert a reg definition." |
| 9755 | () | 9755 | () |
| 9756 | > "reg [" (verilog-sk-datadef)) | 9756 | > "reg [" '(verilog-sk-datadef)) |
| 9757 | 9757 | ||
| 9758 | (define-skeleton verilog-sk-assign | 9758 | (define-skeleton verilog-sk-assign |
| 9759 | "Insert a skeleton assign statement." | 9759 | "Insert a skeleton assign statement." |
| 9760 | () | 9760 | () |
| 9761 | > "assign " (verilog-sk-prompt-name) " = " _ ";" \n) | 9761 | > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n) |
| 9762 | 9762 | ||
| 9763 | (define-skeleton verilog-sk-while | 9763 | (define-skeleton verilog-sk-while |
| 9764 | "Insert a skeleton while loop statement." | 9764 | "Insert a skeleton while loop statement." |
| 9765 | () | 9765 | () |
| 9766 | > "while (" (verilog-sk-prompt-condition) ") begin" \n | 9766 | > "while (" '(verilog-sk-prompt-condition) ") begin" \n |
| 9767 | > _ \n | 9767 | > _ \n |
| 9768 | > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | 9768 | > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) |
| 9769 | 9769 | ||
| 9770 | (define-skeleton verilog-sk-repeat | 9770 | (define-skeleton verilog-sk-repeat |
| 9771 | "Insert a skeleton repeat loop statement." | 9771 | "Insert a skeleton repeat loop statement." |
| 9772 | () | 9772 | () |
| 9773 | > "repeat (" (verilog-sk-prompt-condition) ") begin" \n | 9773 | > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n |
| 9774 | > _ \n | 9774 | > _ \n |
| 9775 | > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | 9775 | > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) |
| 9776 | 9776 | ||
| @@ -9778,9 +9778,9 @@ and the case items." | |||
| 9778 | "Insert a skeleton while loop statement." | 9778 | "Insert a skeleton while loop statement." |
| 9779 | () | 9779 | () |
| 9780 | > "for (" | 9780 | > "for (" |
| 9781 | (verilog-sk-prompt-init) "; " | 9781 | '(verilog-sk-prompt-init) "; " |
| 9782 | (verilog-sk-prompt-condition) "; " | 9782 | '(verilog-sk-prompt-condition) "; " |
| 9783 | (verilog-sk-prompt-inc) | 9783 | '(verilog-sk-prompt-inc) |
| 9784 | ") begin" \n | 9784 | ") begin" \n |
| 9785 | > _ \n | 9785 | > _ \n |
| 9786 | > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | 9786 | > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) |
| @@ -9798,7 +9798,7 @@ and the case items." | |||
| 9798 | '(setq input "state") | 9798 | '(setq input "state") |
| 9799 | > "// State registers for " str | -23 \n | 9799 | > "// State registers for " str | -23 \n |
| 9800 | '(setq verilog-sk-state str) | 9800 | '(setq verilog-sk-state str) |
| 9801 | > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n | 9801 | > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n |
| 9802 | '(setq input nil) | 9802 | '(setq input nil) |
| 9803 | > \n | 9803 | > \n |
| 9804 | > "// State FF for " verilog-sk-state \n | 9804 | > "// State FF for " verilog-sk-state \n |
| @@ -9809,7 +9809,7 @@ and the case items." | |||
| 9809 | > \n | 9809 | > \n |
| 9810 | > "// Next State Logic for " verilog-sk-state \n | 9810 | > "// Next State Logic for " verilog-sk-state \n |
| 9811 | > "always @ ( /*AUTOSENSE*/ ) begin\n" | 9811 | > "always @ ( /*AUTOSENSE*/ ) begin\n" |
| 9812 | > "case (" (verilog-sk-prompt-state-selector) ") " \n | 9812 | > "case (" '(verilog-sk-prompt-state-selector) ") " \n |
| 9813 | > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n ) | 9813 | > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n ) |
| 9814 | resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil) | 9814 | resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil) |
| 9815 | > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)) | 9815 | > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)) |
diff --git a/src/ChangeLog b/src/ChangeLog index fe6031f5a3f..154143c44b6 100644 --- a/src/ChangeLog +++ b/src/ChangeLog | |||
| @@ -1,3 +1,7 @@ | |||
| 1 | 2008-02-01 Stefan Monnier <monnier@iro.umontreal.ca> | ||
| 2 | |||
| 3 | * xfaces.c (face_at_buffer_position): Remove unused vars. | ||
| 4 | |||
| 1 | 2008-02-01 Kenichi Handa <handa@ni.aist.go.jp> | 5 | 2008-02-01 Kenichi Handa <handa@ni.aist.go.jp> |
| 2 | 6 | ||
| 3 | * ccl.c (CCL_WRITE_CHAR): Fix overflow checking. | 7 | * ccl.c (CCL_WRITE_CHAR): Fix overflow checking. |
diff --git a/src/xfaces.c b/src/xfaces.c index 4f3509ebd30..c00dade631b 100644 --- a/src/xfaces.c +++ b/src/xfaces.c | |||
| @@ -8220,8 +8220,6 @@ face_for_overlay_string (w, pos, region_beg, region_end, | |||
| 8220 | struct frame *f = XFRAME (w->frame); | 8220 | struct frame *f = XFRAME (w->frame); |
| 8221 | Lisp_Object attrs[LFACE_VECTOR_SIZE]; | 8221 | Lisp_Object attrs[LFACE_VECTOR_SIZE]; |
| 8222 | Lisp_Object prop, position; | 8222 | Lisp_Object prop, position; |
| 8223 | int i, noverlays; | ||
| 8224 | Lisp_Object *overlay_vec; | ||
| 8225 | Lisp_Object frame; | 8223 | Lisp_Object frame; |
| 8226 | int endpos; | 8224 | int endpos; |
| 8227 | Lisp_Object propname = mouse ? Qmouse_face : Qface; | 8225 | Lisp_Object propname = mouse ? Qmouse_face : Qface; |