(verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT mis-including genvars.

2 files changed, 7 insertions, 1 deletions

diff --git a/lisp/ChangeLog b/lisp/ChangeLog
index 6aefa76f7d7..19488a7810b 100644
--- a/lisp/ChangeLog
+++ b/lisp/ChangeLog
@@ -1,3 +1,8 @@
+2008-03-18  Wilson Snyder  <wsnyder@wsnyder.org>
+
+        * verilog-mode.el (verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT
+        mis-including genvars.
+
 2008-03-18  Stefan Monnier  <monnier@iro.umontreal.ca>
 
         * vc-bzr.el (vc-bzr-log-view-mode, vc-bzr-annotate-command)
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index b24ccdc5bad..40da7e14f0b 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -6071,7 +6071,8 @@ Return a array of [outputs inouts inputs wire reg assign const]."
                 ((or (equal keywd "supply0")
                      (equal keywd "supply1")
                      (equal keywd "supply")
-                     (equal keywd "localparam"))
+                     (equal keywd "localparam")
+                     (equal keywd "genvar"))
                  (unless io (setq vec nil  enum nil  rvalue nil  signed nil  typedefed nil  multidim nil  sig-paren paren
                                   expect-signal 'sigs-const)))
                 ((or (equal keywd "parameter"))