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authorDan Nicolaescu2008-07-30 07:03:17 +0000
committerDan Nicolaescu2008-07-30 07:03:17 +0000
commit4c5e69c61644d3dac7f6328dce320432e296025d (patch)
tree90ce2be86abd158765a5889a7e3e2e972f9edafc
parentf1902fc011f72852fb3ed4ce39b2f2a7ee986227 (diff)
downloademacs-4c5e69c61644d3dac7f6328dce320432e296025d.tar.gz
emacs-4c5e69c61644d3dac7f6328dce320432e296025d.zip
* verilog-mode.el (verilog-do-indent): Remove special indent for
declarations inside a parenthetical list. The code is ill-advised, and doesn't work given user defined types. (verilog-set-auto-endcomments): Enhance function automatic endcomment to support functions that return user defined types. (verilog-mode): Add code to tell which-function-mode minor mode that Verilog supports this feature. (verilog-beg-block-re-ordered, verilog-indent-re) (verilog-forward-sexp, verilog-forward-wa, verilog-calc-1) (verilog-leap-to-head): Support the new virtual and/or protected tasks, as well as extern declarations of tasks for indenting and for foward/backward expression. * verilog-mode (verilog-read-decls): Allow AUTORESET to work with SV 'logic' signals. [Julian Gorfajn] (verilog-auto-inst-column): Make verilog-auto-inst-column customizable. (verilog-string-replace-matches): Avoid recursion with small replacements. (verilog-auto-inst-param-value, verilog-mode-version) (verilog-mode-version-date, verilog-read-inst-param-value) (verilog-auto-inst, verilog-auto-inst-param) (verilog-auto-inst-port, verilog-simplify-range-expression): Add verilog-auto-inst-param-value option for AUTOINST. [David Rogoff] This allows parameters to be replaced with their values, on the expansion of an AUTOINST with Verilog 2001 style parameter settings.
Diffstat
-rw-r--r--lisp/ChangeLog32
-rw-r--r--lisp/progmodes/verilog-mode.el380
2 files changed, 299 insertions, 113 deletions
diff --git a/lisp/ChangeLog b/lisp/ChangeLog
index 30f89ec3fcd..2f7de0c52f2 100644
--- a/lisp/ChangeLog
+++ b/lisp/ChangeLog
@@ -1,3 +1,35 @@
12008-07-30 Michael McNamara <mac@mail.brushroad.com>
2
3 * verilog-mode.el (verilog-do-indent): Remove special indent for
4 declarations inside a parenthetical list. The code is ill-advised,
5 and doesn't work given user defined types.
6 (verilog-set-auto-endcomments): Enhance function automatic
7 endcomment to support functions that return user defined types.
8 (verilog-mode): Add code to tell which-function-mode minor mode
9 that Verilog supports this feature.
10 (verilog-beg-block-re-ordered, verilog-indent-re)
11 (verilog-forward-sexp, verilog-forward-wa, verilog-calc-1)
12 (verilog-leap-to-head): Support the new virtual and/or protected
13 tasks, as well as extern declarations of tasks for indenting and
14 for foward/backward expression.
15
162008-07-30 Wilson Snyder <wsnyder@wsnyder.org>
17
18 * verilog-mode (verilog-read-decls): Allow AUTORESET to work with
19 SV 'logic' signals. [Julian Gorfajn]
20 (verilog-auto-inst-column): Make verilog-auto-inst-column
21 customizable.
22 (verilog-string-replace-matches): Avoid recursion with small
23 replacements.
24 (verilog-auto-inst-param-value, verilog-mode-version)
25 (verilog-mode-version-date, verilog-read-inst-param-value)
26 (verilog-auto-inst, verilog-auto-inst-param)
27 (verilog-auto-inst-port, verilog-simplify-range-expression): Add
28 verilog-auto-inst-param-value option for AUTOINST. [David Rogoff]
29 This allows parameters to be replaced with their values, on the
30 expansion of an AUTOINST with Verilog 2001 style parameter
31 settings.
32
12008-07-30 David Lord <david.lord@phonecoop.coop> 332008-07-30 David Lord <david.lord@phonecoop.coop>
2 34
3 * calendar/timeclock.el (timeclock-day-projects): Change a `cdr' 35 * calendar/timeclock.el (timeclock-day-projects): Change a `cdr'
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index 8ae43f0a59e..f53f566f08f 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -118,9 +118,9 @@
118;;; Code: 118;;; Code:
119 119
120;; This variable will always hold the version number of the mode 120;; This variable will always hold the version number of the mode
121(defconst verilog-mode-version "423" 121(defconst verilog-mode-version "429"
122 "Version of this Verilog mode.") 122 "Version of this Verilog mode.")
123(defconst verilog-mode-release-date "2008-05-07-GNU" 123(defconst verilog-mode-release-date "2008-06-23-GNU"
124 "Release date of this Verilog mode.") 124 "Release date of this Verilog mode.")
125(defconst verilog-mode-release-emacs t 125(defconst verilog-mode-release-emacs t
126 "If non-nil, this version of Verilog mode was released with Emacs itself.") 126 "If non-nil, this version of Verilog mode was released with Emacs itself.")
@@ -830,6 +830,43 @@ the MSB or LSB of a signal inside an AUTORESET."
830 :type 'string) 830 :type 'string)
831(put 'verilog-assignment-delay 'safe-local-variable 'stringp) 831(put 'verilog-assignment-delay 'safe-local-variable 'stringp)
832 832
833(defcustom verilog-auto-inst-param-value nil
834 "*If set, AUTOINST will replace parameters with the parameter value.
835If nil, leave parameters as symbolic names.
836
837Parameters must be in Verilog 2001 format #(...), and if a parameter is not
838listed as such there (as when the default value is acceptable), it will not
839be replaced, and will remain symbolic.
840
841For example, imagine a submodule uses parameters to declare the size of its
842inputs. This is then used by a upper module:
843
844 module InstModule (o,i)
845 parameter WIDTH;
846 input [WIDTH-1:0] i;
847 endmodule
848
849 module ExampInst;
850 InstModule
851 #(PARAM(10))
852 instName
853 (/*AUTOINST*/
854 .i (i[PARAM-1:0]));
855
856Note even though PARAM=10, the AUTOINST has left the parameter as a
857symbolic name. If `verilog-auto-inst-param-value' is set, this will
858instead expand to:
859
860 module ExampInst;
861 InstModule
862 #(PARAM(10))
863 instName
864 (/*AUTOINST*/
865 .i (i[9:0]));"
866 :group 'verilog-mode-auto
867 :type 'boolean)
868(put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-auto-inst-param-value)
869
833(defcustom verilog-auto-inst-vector t 870(defcustom verilog-auto-inst-vector t
834 "*If true, when creating default ports with AUTOINST, use bus subscripts. 871 "*If true, when creating default ports with AUTOINST, use bus subscripts.
835If nil, skip the subscript when it matches the entire bus as declared in 872If nil, skip the subscript when it matches the entire bus as declared in
@@ -849,8 +886,11 @@ regular use to prevent large numbers of merge conflicts."
849 :type 'boolean) 886 :type 'boolean)
850(put 'verilog-auto-inst-template-numbers 'safe-local-variable 'verilog-booleanp) 887(put 'verilog-auto-inst-template-numbers 'safe-local-variable 'verilog-booleanp)
851 888
852(defvar verilog-auto-inst-column 40 889(defcustom verilog-auto-inst-column 40
853 "Column number for first part of auto-inst.") 890 "*Indent-to column number for net name part of AUTOINST created pin."
891 :group 'verilog-mode-indent
892 :type 'integer)
893(put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
854 894
855(defcustom verilog-auto-input-ignore-regexp nil 895(defcustom verilog-auto-input-ignore-regexp nil
856 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp. 896 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
@@ -1225,7 +1265,7 @@ will break, as the o's continuously replace. xa -> x works ok though."
1225 (let ((start 0)) 1265 (let ((start 0))
1226 (while (string-match from-string string start) 1266 (while (string-match from-string string start)
1227 (setq string (replace-match to-string fixedcase literal string) 1267 (setq string (replace-match to-string fixedcase literal string)
1228 start (min (length string) (match-end 0)))) 1268 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1229 string)) 1269 string))
1230 1270
1231(defsubst verilog-string-remove-spaces (string) 1271(defsubst verilog-string-remove-spaces (string)
@@ -1555,21 +1595,21 @@ find the errors."
1555;; verilog-forward-sexp and verilog-calc-indent 1595;; verilog-forward-sexp and verilog-calc-indent
1556 1596
1557(defconst verilog-beg-block-re-ordered 1597(defconst verilog-beg-block-re-ordered
1558 ( concat "\\<" 1598 ( concat "\\(\\<begin\\>\\)" ;1
1559 "\\(begin\\)" ;1 1599 "\\|\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
1560 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2,3 1600 "\\|\\(\\(\\<disable\\>\\s-+\\)?fork\\>\\)" ;4,5
1561 "\\|\\(\\(disable\\s-+\\)?fork\\)" ;4 1601 "\\|\\(\\<class\\>\\)" ;6
1562 "\\|\\(class\\)" ;5 1602 "\\|\\(\\<table\\>\\)" ;7
1563 "\\|\\(table\\)" ;6 1603 "\\|\\(\\<specify\\>\\)" ;8
1564 "\\|\\(specify\\)" ;7 1604 "\\|\\(\\<function\\>\\)" ;9
1565 "\\|\\(function\\)" ;8 1605 "\\|\\(\\<task\\>\\)" ;10
1566 "\\|\\(task\\)" ;9 1606 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;11
1567 "\\|\\(generate\\)" ;10 1607 "\\|\\(\\<generate\\>\\)" ;15
1568 "\\|\\(covergroup\\)" ;11 1608 "\\|\\(\\<covergroup\\>\\)" ;16
1569 "\\|\\(property\\)" ;12 1609 "\\|\\(\\<property\\>\\)" ;17
1570 "\\|\\(\\(rand\\)?sequence\\)" ;13 1610 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;18
1571 "\\|\\(clocking\\)" ;14 1611 "\\|\\(\\<clocking\\>\\)" ;19
1572 "\\>")) 1612 ))
1573 1613
1574(defconst verilog-end-block-ordered-rry 1614(defconst verilog-end-block-ordered-rry
1575 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" 1615 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
@@ -1710,6 +1750,7 @@ find the errors."
1710 "specify" "endspecify" 1750 "specify" "endspecify"
1711 "table" "endtable" 1751 "table" "endtable"
1712 "task" "endtask" 1752 "task" "endtask"
1753 "virtual"
1713 "`case" 1754 "`case"
1714 "`default" 1755 "`default"
1715 "`define" "`undef" 1756 "`define" "`undef"
@@ -2190,23 +2231,24 @@ Use filename, if current buffer being edited shorten to just buffer name."
2190(defun verilog-forward-sexp () 2231(defun verilog-forward-sexp ()
2191 (let ((reg) 2232 (let ((reg)
2192 (md 2) 2233 (md 2)
2193 (st (point))) 2234 (st (point))
2235 (nest 'yes))
2194 (if (not (looking-at "\\<")) 2236 (if (not (looking-at "\\<"))
2195 (forward-word -1)) 2237 (forward-word -1))
2196 (cond 2238 (cond
2197 ((verilog-skip-forward-comment-or-string) 2239 ((verilog-skip-forward-comment-or-string)
2198 (verilog-forward-syntactic-ws)) 2240 (verilog-forward-syntactic-ws))
2199 ((looking-at verilog-beg-block-re-ordered) ;; begin|(case)|xx|(fork)|class|table|specify|function|task|generate|covergroup|property|sequence|clocking 2241 ((looking-at verilog-beg-block-re-ordered)
2200 (cond 2242 (cond
2201 ((match-end 1) ; end 2243 ((match-end 1);
2202 ;; Search forward for matching begin 2244 ;; Search forward for matching end
2203 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" )) 2245 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
2204 ((match-end 2) ; endcase 2246 ((match-end 2)
2205 ;; Search forward for matching case 2247 ;; Search forward for matching endcase
2206 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ) 2248 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2207 (setq md 3) ;; ender is third item in regexp 2249 (setq md 3) ;; ender is third item in regexp
2208 ) 2250 )
2209 ((match-end 4) ; join 2251 ((match-end 4)
2210 ;; might be "disable fork" 2252 ;; might be "disable fork"
2211 (if (or 2253 (if (or
2212 (looking-at verilog-disable-fork-re) 2254 (looking-at verilog-disable-fork-re)
@@ -2219,51 +2261,63 @@ Use filename, if current buffer being edited shorten to just buffer name."
2219 (forward-word) 2261 (forward-word)
2220 (setq reg nil)) 2262 (setq reg nil))
2221 (progn 2263 (progn
2222 ;; Search forward for matching fork 2264 ;; Search forward for matching join
2223 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))) 2265 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))))
2224 ((match-end 5) ; endclass 2266 ((match-end 6)
2225 ;; Search forward for matching class 2267 ;; Search forward for matching endclass
2226 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) 2268 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
2227 ((match-end 6) ; endtable 2269
2228 ;; Search forward for matching table 2270 ((match-end 7)
2229 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) 2271 ;; Search forward for matching endtable
2230 ((match-end 7) ; endspecify 2272 (setq reg "\\<endtable\\>" )
2231 ;; Search forward for matching specify 2273 (setq nest 'no))
2232 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) 2274 ((match-end 8)
2233 ((match-end 8) ; endfunction 2275 ;; Search forward for matching endspecify
2234 ;; Search forward for matching function 2276 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
2235 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) 2277 ((match-end 9)
2236 ((match-end 9) ; endtask 2278 ;; Search forward for matching endfunction
2237 ;; Search forward for matching task 2279 (setq reg "\\<endfunction\\>" )
2238 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) 2280 (setq nest 'no))
2239 ((match-end 10) ; endgenerate 2281 ((match-end 10)
2240 ;; Search forward for matching generate 2282 ;; Search forward for matching endtask
2241 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) 2283 (setq reg "\\<endtask\\>" )
2242 ((match-end 11) ; endgroup 2284 (setq nest 'no))
2243 ;; Search forward for matching covergroup 2285 ((match-end 11)
2244 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )) 2286 ;; Search forward for matching endtask
2245 ((match-end 12) ; endproperty 2287 (setq reg "\\<endtask\\>" )
2246 ;; Search forward for matching property 2288 (setq nest 'no))
2247 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" )) 2289 ((match-end 15)
2248 ((match-end 13) ; endsequence 2290 ;; Search forward for matching endgenerate
2249 ;; Search forward for matching sequence 2291 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
2250 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ) 2292 ((match-end 16)
2251 (setq md 3)) ; 3 to get to endsequence in the reg above 2293 ;; Search forward for matching endgroup
2252 ((match-end 14) ; endclocking 2294 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
2253 ;; Search forward for matching clocking 2295 ((match-end 17)
2254 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))) 2296 ;; Search forward for matching endproperty
2297 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
2298 ((match-end 18)
2299 ;; Search forward for matching endsequence
2300 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
2301 (setq md 3)) ; 3 to get to endsequence in the reg above
2302 ((match-end 19)
2303 ;; Search forward for matching endclocking
2304 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
2255 (if (and reg 2305 (if (and reg
2256 (forward-word 1)) 2306 (forward-word 1))
2257 (catch 'skip 2307 (catch 'skip
2258 (let ((nest 1)) 2308 (if (eq nest 'yes)
2259 (while (verilog-re-search-forward reg nil 'move) 2309 (let ((depth 1))
2260 (cond 2310 (while (verilog-re-search-forward reg nil 'move)
2261 ((match-end md) ; the closer in reg, so we are climbing out 2311 (cond
2262 (setq nest (1- nest)) 2312 ((match-end md) ; the closer in reg, so we are climbing out
2263 (if (= 0 nest) ; we are out! 2313 (setq depth (1- depth))
2264 (throw 'skip 1))) 2314 (if (= 0 depth) ; we are out!
2265 ((match-end 1) ; the opener in reg, so we are deeper now 2315 (throw 'skip 1)))
2266 (setq nest (1+ nest))))))))) 2316 ((match-end 1) ; the opener in reg, so we are deeper now
2317 (setq depth (1+ depth))))))
2318 (if (verilog-re-search-forward reg nil 'move)
2319 (throw 'skip 1))))))
2320
2267 ((looking-at (concat 2321 ((looking-at (concat
2268 "\\(\\<\\(macro\\)?module\\>\\)\\|" 2322 "\\(\\<\\(macro\\)?module\\>\\)\\|"
2269 "\\(\\<primitive\\>\\)\\|" 2323 "\\(\\<primitive\\>\\)\\|"
@@ -4058,8 +4112,26 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
4058 "Show matching nesting block for debugging." 4112 "Show matching nesting block for debugging."
4059 (interactive) 4113 (interactive)
4060 (save-excursion 4114 (save-excursion
4061 (let ((nesting (verilog-calc-1))) 4115 (let* ((type (verilog-calc-1))
4062 (message "You are at nesting %s" nesting)))) 4116 depth)
4117 ;; Return type of block and indent level.
4118 (if (not type)
4119 (setq type 'cpp))
4120 (if (and
4121 verilog-indent-lists
4122 (not (verilog-in-coverage))
4123 (verilog-in-paren))
4124 (setq depth 1)
4125 (cond
4126 ((eq type 'case)
4127 (setq depth (verilog-case-indent-level)))
4128 ((eq type 'statement)
4129 (setq depth (current-column)))
4130 ((eq type 'defun)
4131 (setq depth 0))
4132 (t
4133 (setq depth (verilog-current-indent-level)))))
4134 (message "You are at nesting %s depth %d" type depth))))
4063 4135
4064(defun verilog-calc-1 () 4136(defun verilog-calc-1 ()
4065 (catch 'nesting 4137 (catch 'nesting
@@ -4104,11 +4176,11 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
4104 ; property 4176 ; property
4105 ; ... 4177 ; ...
4106 ; endfunction 4178 ; endfunction
4107 (let ((here (point))) 4179 (verilog-beg-of-statement)
4108 (save-excursion 4180 (if (looking-at verilog-beg-block-re-ordered)
4109 (verilog-beg-of-statement) 4181 (throw 'nesting 'block)
4110 (if (= (point) here) 4182 (throw 'nesting 'defun)))
4111 (throw 'nesting 'block))))) 4183
4112 (t (throw 'nesting 'block)))) 4184 (t (throw 'nesting 'block))))
4113 4185
4114 ((looking-at verilog-end-block-re) 4186 ((looking-at verilog-end-block-re)
@@ -4180,12 +4252,17 @@ of the appropriate enclosing block."
4180Jump from end to matching begin, from endcase to matching case, and so on." 4252Jump from end to matching begin, from endcase to matching case, and so on."
4181 (let ((reg nil) 4253 (let ((reg nil)
4182 snest 4254 snest
4255 (nesting 'yes)
4183 (nest 1)) 4256 (nest 1))
4184 (cond 4257 (cond
4185 ((looking-at "\\<end\\>") 4258 ((looking-at "\\<end\\>")
4186 ;; 1: Search back for matching begin 4259 ;; 1: Search back for matching begin
4187 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|" 4260 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
4188 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))) 4261 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
4262 ((looking-at "\\<endtask\\>")
4263 ;; 9: Search back for matching task
4264 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
4265 (setq nesting 'no))
4189 ((looking-at "\\<endcase\\>") 4266 ((looking-at "\\<endcase\\>")
4190 ;; 2: Search back for matching case 4267 ;; 2: Search back for matching case
4191 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" )) 4268 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
@@ -4207,9 +4284,6 @@ Jump from end to matching begin, from endcase to matching case, and so on."
4207 ((looking-at "\\<endgenerate\\>") 4284 ((looking-at "\\<endgenerate\\>")
4208 ;; 8: Search back for matching generate 4285 ;; 8: Search back for matching generate
4209 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) 4286 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4210 ((looking-at "\\<endtask\\>")
4211 ;; 9: Search back for matching task
4212 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4213 ((looking-at "\\<endgroup\\>") 4287 ((looking-at "\\<endgroup\\>")
4214 ;; 10: Search back for matching covergroup 4288 ;; 10: Search back for matching covergroup
4215 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )) 4289 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
@@ -4227,32 +4301,41 @@ Jump from end to matching begin, from endcase to matching case, and so on."
4227 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))) 4301 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
4228 (if reg 4302 (if reg
4229 (catch 'skip 4303 (catch 'skip
4230 (let (sreg) 4304 (if (eq nesting 'yes)
4231 (while (verilog-re-search-backward reg nil 'move) 4305 (let (sreg)
4232 (cond 4306 (while (verilog-re-search-backward reg nil 'move)
4233 ((match-end 1) ; begin 4307 (cond
4234 (setq nest (1- nest)) 4308 ((match-end 1) ; begin
4235 (if (= 0 nest) 4309 (setq nest (1- nest))
4236 ;; Now previous line describes syntax 4310 (if (= 0 nest)
4237 (throw 'skip 1)) 4311 ;; Now previous line describes syntax
4238 (if (and snest 4312 (throw 'skip 1))
4239 (= snest nest)) 4313 (if (and snest
4240 (setq reg sreg))) 4314 (= snest nest))
4241 ((match-end 2) ; end 4315 (setq reg sreg)))
4242 (setq nest (1+ nest))) 4316 ((match-end 2) ; end
4243 ((match-end 3) 4317 (setq nest (1+ nest)))
4244 ;; endcase, jump to case 4318 ((match-end 3)
4245 (setq snest nest) 4319 ;; endcase, jump to case
4246 (setq nest (1+ nest)) 4320 (setq snest nest)
4247 (setq sreg reg) 4321 (setq nest (1+ nest))
4248 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) 4322 (setq sreg reg)
4249 ((match-end 4) 4323 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4250 ;; join, jump to fork 4324 ((match-end 4)
4251 (setq snest nest) 4325 ;; join, jump to fork
4252 (setq nest (1+ nest)) 4326 (setq snest nest)
4253 (setq sreg reg) 4327 (setq nest (1+ nest))
4254 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) 4328 (setq sreg reg)
4255 ))))))) 4329 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4330 )))
4331 ;no nesting
4332 (if (and
4333 (verilog-re-search-backward reg nil 'move)
4334 (match-end 1)) ; task -> could be virtual and/or protected
4335 (progn
4336 (verilog-beg-of-statement)
4337 (throw 'skip 1))
4338 (throw 'skip 1)))))))
4256 4339
4257(defun verilog-continued-line () 4340(defun verilog-continued-line ()
4258 "Return true if this is a continued line. 4341 "Return true if this is a continued line.
@@ -6047,6 +6130,33 @@ Ignore width if optional NO-WIDTH is set."
6047 ;; Important: don't use match string, this must work with Emacs 19 font-lock on 6130 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6048 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) 6131 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6049 6132
6133(defun verilog-read-inst-param-value ()
6134 "Return list of parameters and values when point is inside instantiation."
6135 (save-excursion
6136 (verilog-read-inst-backward-name)
6137 ;; Skip over instantiation name
6138 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6139 ;; If there are parameterized instantiations
6140 (when (looking-at ")")
6141 (let ((end-pt (point))
6142 params
6143 param-name paren-beg-pt param-value)
6144 (verilog-backward-open-paren)
6145 (while (verilog-re-search-forward-quick "\\." end-pt t)
6146 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
6147 (skip-chars-backward "a-zA-Z0-9'_$")
6148 (looking-at "[a-zA-Z0-9`_\$]+")
6149 (setq param-name (buffer-substring-no-properties
6150 (match-beginning 0) (match-end 0)))
6151 (verilog-re-search-forward-quick "(" nil nil)
6152 (setq paren-beg-pt (point))
6153 (verilog-forward-close-paren)
6154 (setq param-value (verilog-string-remove-spaces
6155 (buffer-substring-no-properties
6156 paren-beg-pt (1- (point)))))
6157 (setq params (cons (list param-name param-value) params)))
6158 params))))
6159
6050(defun verilog-read-auto-params (num-param &optional max-param) 6160(defun verilog-read-auto-params (num-param &optional max-param)
6051 "Return parameter list inside auto. 6161 "Return parameter list inside auto.
6052Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters." 6162Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
@@ -6152,8 +6262,9 @@ Return a array of [outputs inouts inputs wire reg assign const]."
6152 (equal keywd "tri1")) 6262 (equal keywd "tri1"))
6153 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren 6263 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6154 expect-signal 'sigs-wire))) 6264 expect-signal 'sigs-wire)))
6155 ((or (equal keywd "reg") 6265 ((member keywd (list "reg" "trireg"
6156 (equal keywd "trireg")) 6266 "byte" "shortint" "int" "longint" "integer" "time"
6267 "bit" "logic"))
6157 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren 6268 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6158 expect-signal 'sigs-reg))) 6269 expect-signal 'sigs-reg)))
6159 ((equal keywd "assign") 6270 ((equal keywd "assign")
@@ -7609,6 +7720,28 @@ This repairs those mis-inserted by a AUTOARG."
7609 (t nil))))) 7720 (t nil)))))
7610;;(verilog-make-width-expression "`A:`B") 7721;;(verilog-make-width-expression "`A:`B")
7611 7722
7723(defun verilog-simplify-range-expression (range-exp)
7724 "Return a simplified range expression with constants eliminated from RANGE-EXP."
7725 (let ((out range-exp)
7726 (last-pass ""))
7727 (while (not (equal last-pass out))
7728 (setq last-pass out)
7729 (while (string-match "(\\<\\([0-9]+\\)\\>)" out)
7730 (setq out (replace-match "\\1" nil nil out)))
7731 (while (string-match "\\<\\([0-9]+\\)\\>\\s *\\+\\s *\\<\\([0-9]+\\)\\>" out)
7732 (setq out (replace-match
7733 (int-to-string (+ (string-to-number (match-string 1 out))
7734 (string-to-number (match-string 2 out))))
7735 nil nil out)))
7736 (while (string-match "\\<\\([0-9]+\\)\\>\\s *\\-\\s *\\<\\([0-9]+\\)\\>" out)
7737 (setq out (replace-match
7738 (int-to-string (- (string-to-number (match-string 1 out))
7739 (string-to-number (match-string 2 out))))
7740 nil nil out))))
7741 out))
7742;;(verilog-simplify-range-expression "1")
7743;;(verilog-simplify-range-expression "(((16)+1)-3)")
7744
7612(defun verilog-typedef-name-p (variable-name) 7745(defun verilog-typedef-name-p (variable-name)
7613 "Return true if the VARIABLE-NAME is a type definition." 7746 "Return true if the VARIABLE-NAME is a type definition."
7614 (when verilog-typedef-regexp 7747 (when verilog-typedef-regexp
@@ -8041,12 +8174,13 @@ Avoid declaring ports manually, as it makes code harder to maintain."
8041(defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning 8174(defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
8042(defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning 8175(defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
8043 8176
8044(defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star) 8177(defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
8045 "Print out a instantiation connection for this PORT-ST. 8178 "Print out a instantiation connection for this PORT-ST.
8046Insert to INDENT-PT, use template TPL-LIST. 8179Insert to INDENT-PT, use template TPL-LIST.
8047@ are instantiation numbers, replaced with TPL-NUM. 8180@ are instantiation numbers, replaced with TPL-NUM.
8048@\"(expression @)\" are evaluated, with @ as a variable. 8181@\"(expression @)\" are evaluated, with @ as a variable.
8049If FOR-STAR add comment it is a .* expansion." 8182If FOR-STAR add comment it is a .* expansion.
8183If PAR-VALUES replace final strings with these parameter values."
8050 (let* ((port (verilog-sig-name port-st)) 8184 (let* ((port (verilog-sig-name port-st))
8051 (tpl-ass (or (assoc port (car tpl-list)) 8185 (tpl-ass (or (assoc port (car tpl-list))
8052 (verilog-auto-inst-port-map port-st))) 8186 (verilog-auto-inst-port-map port-st)))
@@ -8064,7 +8198,18 @@ If FOR-STAR add comment it is a .* expansion."
8064 (concat port "/*" (verilog-sig-multidim-string port-st) 8198 (concat port "/*" (verilog-sig-multidim-string port-st)
8065 vl-bits "*/") 8199 vl-bits "*/")
8066 (concat port vl-bits))) 8200 (concat port vl-bits)))
8067 (case-fold-search nil)) 8201 (case-fold-search nil)
8202 (check-values par-values))
8203 ;; Replace parameters in bit-width
8204 (when (and check-values
8205 (not (equal vl-bits "")))
8206 (while check-values
8207 (setq vl-bits (verilog-string-replace-matches
8208 (concat "\\<" (nth 0 (car check-values)) "\\>")
8209 (concat "(" (nth 1 (car check-values)) ")")
8210 t t vl-bits)
8211 check-values (cdr check-values)))
8212 (setq vl-bits (verilog-simplify-range-expression vl-bits))) ; Not in the loop for speed
8068 ;; Find template 8213 ;; Find template
8069 (cond (tpl-ass ; Template of exact port name 8214 (cond (tpl-ass ; Template of exact port name
8070 (setq tpl-net (nth 1 tpl-ass))) 8215 (setq tpl-net (nth 1 tpl-ass)))
@@ -8098,6 +8243,7 @@ If FOR-STAR add comment it is a .* expansion."
8098 ;; Replace @ and [] magic variables in final output 8243 ;; Replace @ and [] magic variables in final output
8099 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net)) 8244 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
8100 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))) 8245 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
8246 ;; Insert it
8101 (indent-to indent-pt) 8247 (indent-to indent-pt)
8102 (insert "." port) 8248 (insert "." port)
8103 (indent-to verilog-auto-inst-column) 8249 (indent-to verilog-auto-inst-column)
@@ -8173,6 +8319,9 @@ Limitations:
8173 8319
8174 SystemVerilog multidimensional input/output has only experimental support. 8320 SystemVerilog multidimensional input/output has only experimental support.
8175 8321
8322 Parameters referenced by the instantiation will remain symbolic, unless
8323 `verilog-auto-inst-param-value' is set.
8324
8176For example, first take the submodule InstModule.v: 8325For example, first take the submodule InstModule.v:
8177 8326
8178 module InstModule (o,i) 8327 module InstModule (o,i)
@@ -8415,7 +8564,8 @@ Lisp Templates:
8415 (vector-skip-list (unless verilog-auto-inst-vector 8564 (vector-skip-list (unless verilog-auto-inst-vector
8416 (verilog-decls-get-signals moddecls))) 8565 (verilog-decls-get-signals moddecls)))
8417 submod submodi submoddecls 8566 submod submodi submoddecls
8418 inst skip-pins tpl-list tpl-num did-first) 8567 inst skip-pins tpl-list tpl-num did-first par-values)
8568
8419 ;; Find module name that is instantiated 8569 ;; Find module name that is instantiated
8420 (setq submod (verilog-read-inst-module) 8570 (setq submod (verilog-read-inst-module)
8421 inst (verilog-read-inst-name) 8571 inst (verilog-read-inst-name)
@@ -8426,6 +8576,10 @@ Lisp Templates:
8426 ;; Parse any AUTO_LISP() before here 8576 ;; Parse any AUTO_LISP() before here
8427 (verilog-read-auto-lisp (point-min) pt) 8577 (verilog-read-auto-lisp (point-min) pt)
8428 8578
8579 ;; Read parameters (after AUTO_LISP)
8580 (setq par-values (and verilog-auto-inst-param-value
8581 (verilog-read-inst-param-value)))
8582
8429 ;; Lookup position, etc of submodule 8583 ;; Lookup position, etc of submodule
8430 ;; Note this may raise an error 8584 ;; Note this may raise an error
8431 (when (setq submodi (verilog-modi-lookup submod t)) 8585 (when (setq submodi (verilog-modi-lookup submod t))
@@ -8450,7 +8604,7 @@ Lisp Templates:
8450 (insert "// Outputs\n") 8604 (insert "// Outputs\n")
8451 (mapc (lambda (port) 8605 (mapc (lambda (port)
8452 (verilog-auto-inst-port port indent-pt 8606 (verilog-auto-inst-port port indent-pt
8453 tpl-list tpl-num for-star)) 8607 tpl-list tpl-num for-star par-values))
8454 sig-list))) 8608 sig-list)))
8455 (let ((sig-list (verilog-signals-not-in 8609 (let ((sig-list (verilog-signals-not-in
8456 (verilog-decls-get-inouts submoddecls) 8610 (verilog-decls-get-inouts submoddecls)
@@ -8462,7 +8616,7 @@ Lisp Templates:
8462 (insert "// Inouts\n") 8616 (insert "// Inouts\n")
8463 (mapc (lambda (port) 8617 (mapc (lambda (port)
8464 (verilog-auto-inst-port port indent-pt 8618 (verilog-auto-inst-port port indent-pt
8465 tpl-list tpl-num for-star)) 8619 tpl-list tpl-num for-star par-values))
8466 sig-list))) 8620 sig-list)))
8467 (let ((sig-list (verilog-signals-not-in 8621 (let ((sig-list (verilog-signals-not-in
8468 (verilog-decls-get-inputs submoddecls) 8622 (verilog-decls-get-inputs submoddecls)
@@ -8474,7 +8628,7 @@ Lisp Templates:
8474 (insert "// Inputs\n") 8628 (insert "// Inputs\n")
8475 (mapc (lambda (port) 8629 (mapc (lambda (port)
8476 (verilog-auto-inst-port port indent-pt 8630 (verilog-auto-inst-port port indent-pt
8477 tpl-list tpl-num for-star)) 8631 tpl-list tpl-num for-star par-values))
8478 sig-list))) 8632 sig-list)))
8479 ;; Kill extra semi 8633 ;; Kill extra semi
8480 (save-excursion 8634 (save-excursion
@@ -8581,7 +8735,7 @@ Templates:
8581 (insert "// Parameters\n") 8735 (insert "// Parameters\n")
8582 (mapc (lambda (port) 8736 (mapc (lambda (port)
8583 (verilog-auto-inst-port port indent-pt 8737 (verilog-auto-inst-port port indent-pt
8584 tpl-list tpl-num nil)) 8738 tpl-list tpl-num nil nil))
8585 sig-list))) 8739 sig-list)))
8586 ;; Kill extra semi 8740 ;; Kill extra semi
8587 (save-excursion 8741 (save-excursion
generated by cgit v1.2.1 (git 2.18.0) at 2026-02-13 22:54:08 +0000