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authorWilson Snyder2015-09-18 08:29:32 -0400
committerWilson Snyder2015-09-18 08:29:32 -0400
commit17e5f43697992a0a3d3607013ee55b17b680f989 (patch)
treeeae94b7a92014d651c24cd5e4909363e54cba817
parentfb875ee6ff20034944df04b83a147493db7ddeb3 (diff)
downloademacs-17e5f43697992a0a3d3607013ee55b17b680f989.tar.gz
emacs-17e5f43697992a0a3d3607013ee55b17b680f989.zip
/svaha/wsnyder/d/log
-rw-r--r--lisp/progmodes/verilog-mode.el12
1 files changed, 6 insertions, 6 deletions
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index 58ffba3dddb..3baf768052c 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -841,7 +841,7 @@ first difference.")
841 (verilog-xl-2 841 (verilog-xl-2
842 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3) 842 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
843 (verilog-IES 843 (verilog-IES
844 ".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3) 844 ".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
845 (verilog-surefire-1 845 (verilog-surefire-1
846 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2) 846 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
847 (verilog-surefire-2 847 (verilog-surefire-2
@@ -885,8 +885,8 @@ See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
885 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t) 885 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
886 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t) 886 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
887 ;; verilog-IES (nc-verilog) 887 ;; verilog-IES (nc-verilog)
888 (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t) 888 (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
889 (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t) 889 (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
890 ;; verilog-surefire-1 890 ;; verilog-surefire-1
891 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t) 891 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
892 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t) 892 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
@@ -2303,7 +2303,7 @@ find the errors."
2303 ;; non blocking assignment operator 2303 ;; non blocking assignment operator
2304 "<=" 2304 "<="
2305 ;; comparison 2305 ;; comparison
2306 "==" "!=" "===" "!==" "<=" ">=" "==\\?" "!=\\?" "<->" 2306 "==" "!=" "===" "!==" "<=" ">=" "==?" "!=?" "<->"
2307 ;; event_trigger 2307 ;; event_trigger
2308 "->" "->>" 2308 "->" "->>"
2309 ;; property_expr 2309 ;; property_expr
@@ -9674,7 +9674,7 @@ If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9674 ;; something like a[b]. Sorry, it should be substituted into the parser 9674 ;; something like a[b]. Sorry, it should be substituted into the parser
9675 (setq symbol 9675 (setq symbol
9676 (verilog-string-replace-matches 9676 (verilog-string-replace-matches
9677 "\\[[^0-9: \t]+]" "" nil nil 9677 "\\[[^0-9: \t]+\\]" "" nil nil
9678 (or (verilog-symbol-detick symbol nil) 9678 (or (verilog-symbol-detick symbol nil)
9679 (if verilog-auto-sense-defines-constant 9679 (if verilog-auto-sense-defines-constant
9680 "0" 9680 "0"
@@ -11153,7 +11153,7 @@ If PAR-VALUES replace final strings with these parameter values."
11153 (for-star 11153 (for-star
11154 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) 11154 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11155 verilog-auto-inst-column)) 11155 verilog-auto-inst-column))
11156 (verilog-insert " // Implicit .*\n")) 11156 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
11157 (t 11157 (t
11158 (insert "\n"))))) 11158 (insert "\n")))))
11159;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3") 11159;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")